PIC16F627A-I/ML Microchip Technology, PIC16F627A-I/ML Datasheet
PIC16F627A-I/ML
Specifications of PIC16F627A-I/ML
PIC16F627A-I/MLR
Related parts for PIC16F627A-I/ML
PIC16F627A-I/ML Summary of contents
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... Microcontrollers with nanoWatt Technology © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Flash-Based, 8-Bit CMOS Data Sheet DS40044G ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Flash (words) PIC16F627A 1024 PIC16F628A 2048 PIC16F648A 4096 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Low-Power Features: • Standby Current: - 100 nA @ 2.0V, typical • Operating Current μ kHz, 2.0V, typical - 120 μ MHz, 2.0V, typical • Watchdog Timer Current μA @ 2.0V, typical • ...
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... Pin Diagrams PDIP, SOIC RA2/AN2/V RA3/AN3/CMP1 RA4/T0CKI/CMP2 RA5/MCLR/V RB0/INT RB1/RX/DT RB2/TX/CK RB3/CCP1 SSOP PIC16F627A/628A/648A DS40044G-page RA1/AN1 REF 17 RA0/AN0 RA7/OSC1/CLKIN 4 RA6/OSC2/CLKOUT RB7/T1OSI/PGD RB6/T1OSO/T1CKI/PGC 8 RB5 RB4/PGM 28-Pin QFN RA5/MCLR PIC16F627A/628A NC 4 PIC16F648A RB0/INT 7 21 RA7/OSC1/CLKIN 20 RA6/OSC2/CLKOUT RB7/T1OSI/PGD 15 RB6/T1OSO/T1CKI/PGC © 2009 Microchip Technology Inc. ...
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... Table of Contents 1.0 General Description ........................................................................................................................................................................ 7 2.0 PIC16F627A/628A/648A Device Varieties...................................................................................................................................... 9 3.0 Architectural Overview .................................................................................................................................................................. 11 4.0 Memory Organization .................................................................................................................................................................... 17 5.0 I/O Ports ........................................................................................................................................................................................ 33 6.0 Timer0 Module .............................................................................................................................................................................. 47 7.0 Timer1 Module .............................................................................................................................................................................. 50 8.0 Timer2 Module .............................................................................................................................................................................. 54 9.0 Capture/Compare/PWM (CCP) Module ........................................................................................................................................ 57 10.0 Comparator Module .................................................................................................................................................................... 63 11.0 Voltage Reference Module ......................................................................................................................................................... 69 12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Module......................................................................... 73 13 ...
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... PIC16F627A/628A/648A NOTES: DS40044G-page 6 © 2009 Microchip Technology Inc. ...
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... All PIC family devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect and high I/O current capability. All PIC16F627A/628A/648A family devices use serial programming with clock pin RB6 and data pin RB7. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A The HS mode is for High-Speed crystals. The EC mode is for an external clock source ...
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... PIC16F627A/628A/648A NOTES: DS40044G-page 8 © 2009 Microchip Technology Inc. ...
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... A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16F627A/628A/648A Product Identification System, at the end of this data sheet. When placing orders, please use this page of the data sheet to specify the correct part number. ...
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... PIC16F627A/628A/648A NOTES: DS40044G-page 10 © 2009 Microchip Technology Inc. ...
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... This symmetrical nature and lack of ‘special optimal situations’ makes programming with the PIC16F627A/628A/648A addition, the learning curve is reduced significantly. The PIC16F627A/628A/648A devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file ...
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... PIC16F627A/628A/648A FIGURE 3-1: BLOCK DIAGRAM 13 Program Counter Flash Program Memory Program 14 Bus Instruction Reg Direct Addr 8 Instruction Decode & Start-up Timer Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Programming MCLR Timer0 Comparator V CCP1 REF Higher order bits are from the Status register. Note ...
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... TABLE 3-2: PIC16F627A/628A/648A PINOUT DESCRIPTION Name Function RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/V RA2 REF AN2 V REF RA3/AN3/CMP1 RA3 AN3 CMP1 RA4/T0CKI/CMP2 RA4 T0CKI CMP2 RA5/MCLR/V RA5 PP MCLR V PP RA6/OSC2/CLKOUT RA6 OSC2 CLKOUT RA7/OSC1/CLKIN RA7 OSC1 CLKIN RB0/INT RB0 INT ...
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... PIC16F627A/628A/648A TABLE 3-2: PIC16F627A/628A/648A PINOUT DESCRIPTION (CONTINUED) Name Function RB4/PGM RB4 PGM RB5 RB5 RB6/T1OSO/T1CKI/PGC RB6 T1OSO T1CKI PGC RB7/T1OSI/PGD RB7 T1OSI PGD Output Legend: — = Not used TTL = TTL Input DS40044G-page 14 Input Type Output Type TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. ...
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... All instructions are single cycle except for any program branches. These take two cycles since the fetch Note: instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 3.2 Instruction Flow/Pipelining An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4) ...
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... PIC16F627A/628A/648A NOTES: DS40044G-page 16 © 2009 Microchip Technology Inc. ...
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... Program Memory Organization The PIC16F627A/628A/648A has a 13-bit program counter capable of addressing program memory space. Only the first (0000h-03FFh) for the PIC16F627A (0000h-07FFh) for the PIC16F628A and (0000h-0FFFh) for the PIC16F648A are physically implemented. Accessing a location above these boundaries will cause a wrap- ...
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... PIC16F627A/628A/648A FIGURE 4-2: DATA MEMORY MAP OF THE PIC16F627A AND PIC16F628A (1) Indirect addr. 00h Indirect addr. 01h TMR0 PCL 02h 03h STATUS 04h FSR PORTA 05h PORTB 06h 07h 08h 09h PCLATH 0Ah 0Bh INTCON PIR1 0Ch 0Dh 0Eh TMR1L TMR1H 0Fh ...
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... CMCON 20h General Purpose Register 80 Bytes 6Fh 70h 16 Bytes 7Fh Bank 0 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A (1) (1) Indirect addr. 80h TMR0 OPTION 81h PCL PCL 82h STATUS STATUS 83h ...
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... PIC16F627A/628A/648A 4.2.2 SPECIAL FUNCTION REGISTERS The SFRs are registers used by the CPU and Periph- eral functions for controlling the desired operation of the device (Table 4-3). These registers are static RAM. The special registers can be classified into two sets (core and peripheral). The SFRs associated with the “ ...
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... VROE - = Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Legend: For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7. Note 1: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 T0CS T0SE PSA ...
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... PIC16F627A/628A/648A TABLE 4-5: SPECIAL FUNCTION REGISTERS SUMMARY BANK2 Address Name Bit 7 Bit 6 Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx Timer0 Module’s Register 101h TMR0 102h PCL Program Counter’s (PC) Least Significant Byte ...
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... Unimplemented - = Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Legend: For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7. Note 1: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 T0CS T0SE PSA ...
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... PIC16F627A/628A/648A 4.2.2.1 Status Register The Status register, shown in Register 4-1, contains the arithmetic status of the ALU; the Reset status and the bank select bits for data memory (SRAM). The Status register can be the destination for any instruction, like any other register. If the Status register ...
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... Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC16F627A/628A/648A To achieve a 1:1 prescaler assignment for Note: TMR0, assign the prescaler to the WDT (PSA = 1). See Section 6.3.1 “Switching Prescaler Assignment”. R/W-1 R/W-1 R/W-1 T0CS ...
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... PIC16F627A/628A/648A 4.2.2.3 INTCON Register The INTCON register is a readable and writable register, which contains the various enable and flag bits for all interrupt sources except the comparator module. See Section 4.2.2.4 “PIE1 Register” Section 4.2.2.5 “PIR1 Register” for a description of the comparator enable and flag bits ...
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... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC16F627A/628A/648A R/W-0 R/W-0 U-0 RCIE TXIE — CCP1IE W = Writable bit U = Unimplemented bit, read as ‘ ...
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... PIC16F627A/628A/648A 4.2.2.5 PIR1 Register This register contains interrupt flag bits. REGISTER 4-5: PIR1 – PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch) R/W-0 R/W-0 EEIF CMIF bit 7 bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software The write operation has not completed or has not been started ...
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... A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC16F627A/628A/648A BOR is unknown on Power-on Reset. It Note: must then be set by the user and checked on subsequent Resets to see if BOR is cleared, indicating a brown-out has occurred. The BOR Status bit is a “ ...
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... Application Note AN556 “Implementing a Table Read” (DS00556). 4.3.2 STACK The PIC16F627A/628A/648A family has an 8-level deep x 13-bit wide hardware stack (Figure 4-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch ...
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... FIGURE 4-5: DIRECT/INDIRECT ADDRESSING PIC16F627A/628A/648A Status Direct Addressing Register RP1 RP0 6 from opcode bank select location select 00h RAM File Registers 7Fh Bank 0 For memory map detail see Figure 4-3, Figure 4-2 and Figure 4-1. Note: © 2009 Microchip Technology Inc. ...
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... PIC16F627A/628A/648A NOTES: DS40044G-page 32 © 2009 Microchip Technology Inc. ...
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... I/O PORTS The PIC16F627A/628A/648A have two ports, PORTA and PORTB. Some pins for these I/O ports are multiplexed with alternate functions for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. ...
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... PIC16F627A/628A/648A FIGURE 5-2: BLOCK DIAGRAM OF RA2/AN2/V REF Data Bus PORTA CK Q Data Latch TRISA Analog CK Q Input Mode TRIS Latch (CMCON Reg.) RD Schmitt Trigger TRISA Input Buffer PORTA To Comparator VROE V REF FIGURE 5-3: BLOCK DIAGRAM OF THE RA3/AN3/CMP1 PIN Data Bus D Q Comparator Output ...
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... Bit) MCLR circuit MCLR Filter Schmitt Trigger Program Input Buffer mode HV Detect Data Bus RD V TRISA PORTA © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Comparator Mode = 110 (CMCON Reg FIGURE 5-6: PIN PP From OSC1 CLKOUT(F OSC D WR PORTA OSC Data Latch (2) ...
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... PIC16F627A/628A/648A FIGURE 5-7: BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN To Clock Circuits Data Bus PORTA CK Q Data Latch TRISA CK Q TRIS Latch RD TRISA F = 100, 101 (1) OSC RD PORTA Note 1: INTOSC with CLKOUT and INTOSC with I/O. DS40044G-page Schmitt Trigger Input Buffer RA7/OSC1/CLKIN Pin V SS © 2009 Microchip Technology Inc. ...
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... VREN VROE - = Unimplemented locations read as ‘0’ unchanged unknown value depends on condition. Shaded cells Legend: are not used for PORTA. MCLRE configuration bit sets RA5 functionality. Note 1: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Output Type ST CMOS Bidirectional I/O port AN — Analog comparator input ...
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... PIC16F627A/628A/648A 5.2 PORTB and TRISB Registers PORTB is an 8-bit wide bidirectional port. The corresponding data direction register is TRISB. A ‘1’ in the TRISB register puts the corresponding output driver in a High-impedance mode. A ‘0’ in the TRISB register puts the contents of the output latch on the selected pin(s) ...
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... Peripheral OE TTL Input RD TRISB Buffer PORTB USART Receive Input Schmitt Trigger Peripheral OE (output enable) is only active if Note 1: peripheral select is active. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A FIGURE 5-10 Weak RBPU Pull-up P SPEN V DD USART TX/CK Output Data Bus RB1/ RX/DT WR PORTB V ...
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... PIC16F627A/628A/648A FIGURE 5-11: BLOCK DIAGRAM OF RB3/CCP1 PIN RBPU CCP1CON CCP output 0 Data Bus PORTB CK Q Data Latch TRISB CK Q TRIS Latch (2) Peripheral OE RD TRISB PORTB CCP In Schmitt Trigger Peripheral OE (output enable) is only active if Note 1: peripheral select is active. DS40044G-page Weak Pull- RB3/ ...
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... Data Latch D WR TRISB CK TRIS Latch RD TRISB LVP (Configuration Bit) RD PORTB PGM input Set RBIF From other RB<7:4> pins The low-voltage programming disables the interrupt-on-change and the weak pull-ups on RB4. Note: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Schmitt Trigger weak pull- RB4/PGM ...
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... PIC16F627A/628A/648A FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN RBPU Data Bus PORTB CK Q Data Latch TRISB CK Q TRIS Latch RD TRISB RD PORTB Set RBIF From other RB<7:4> pins DS40044G-page weak DD P pull- TTL input buffer © 2009 Microchip Technology Inc. RB5 pin ...
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... FIGURE 5-14: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI/PGC PIN RBPU Data Bus WR PORTB WR TRISB TRIS Latch RD TRISB T1OSCEN RD PORTB TMR1 Clock From RB7 Serial Programming Clock Set RBIF © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Data Latch Schmitt Trigger From other RB<7:4> pins weak pull-up ...
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... PIC16F627A/628A/648A FIGURE 5-15: BLOCK DIAGRAM OF THE RB7/T1OSI/PGD PIN RBPU To RB6 Data Bus WR PORTB WR TRISB RD TRISB T10SCEN RD PORTB Serial Programming Input Set RBIF DS40044G-page Data Latch TRIS Latch Q Q From other RB<7:4> pins weak pull-up P TMR1 oscillator V DD RB7/T1OSI/ PGD pin V SS ...
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... OPTION RBPU INTEDG u = unchanged unknown. Shaded cells are not used for PORTB. Legend: LVP configuration bit sets RB4 functionality. Note 1: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Output Type TTL CMOS Bidirectional I/O port. Can be software programmed for internal weak pull-up. ST — ...
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... PIC16F627A/628A/648A 5.3 I/O Programming Considerations 5.3.1 BIDIRECTIONAL I/O PORTS Any instruction that writes operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register ...
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... The Timer0 interrupt cannot wake the processor from Sleep since the timer is shut off during Sleep. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 6.2 Using Timer0 with External Clock When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (T synchronization ...
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... PIC16F627A/628A/648A 6.3 Timer0 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module postscaler for the Watchdog Timer. A prescaler assignment for the Timer0 module means that there is no postscaler for the Watchdog Timer, and vice-versa. FIGURE 6-1: BLOCK DIAGRAM OF THE TIMER0/WDT ...
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... Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used for Timer0. Legend: Option is referred by OPTION_REG in MPLAB Note 1: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 6-2. This precaution must be taken even if the WDT is disabled. EXAMPLE 6-2: ...
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... Timer1 also has an internal “Reset input”. This Reset can be generated by the CCP module (Section 9.0 “Capture/Compare/PWM Register 7-1 shows the Timer1 control register. For the PIC16F627A/628A/648A, when the Timer1 oscillator is enabled (T1OSCEN is set), the RB7/ T1OSI/PGD become inputs. That is, the TRISB<7:6> value is ignored ...
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... T1OSC RB6/T1OSO/T1CKI/PGC RB7/T1OSI/PGD Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 7.2.1 EXTERNAL CLOCK INPUT TIMING FOR SYNCHRONIZED COUNTER MODE When an external clock input is used for Timer1 in Synchronized Counter mode, it must meet certain requirements ...
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... PIC16F627A/628A/648A 7.3 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 7.3.2 “ ...
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... T1CKPS1 x = unknown unchanged unimplemented read as ‘0’. Shaded cells are not used by the Timer1 module. Legend: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 7.5 Resetting Timer1 Using a CCP Trigger Output If the CCP1 module is configured in Compare mode to generate a “special event trigger” (CCP1M<3:0> = 1011), this signal will reset Timer1 ...
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... PIC16F627A/628A/648A 8.0 TIMER2 MODULE Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time base for PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device Reset. The input clock (F /4) has a prescale option of 1:1, OSC 1:4 or 1:16, selected by control bits T2CKPS< ...
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... TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 92h PR2 Timer2 Period Register x = unknown unchanged unimplemented read as ‘0’. Shaded cells are not used by the Timer2 module. Legend: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A R/W-0 R/W-0 R/W-0 TOUTPS0 W = Writable bit U = Unimplemented bit, read as ‘0’ ...
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... PIC16F627A/628A/648A NOTES: DS40044G-page 56 © 2009 Microchip Technology Inc. ...
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... Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 11xx = PWM mode Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC16F627A/628A/648A TABLE 9-1: CCP Mode Capture Compare PWM (CCPR1) is ...
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... PIC16F627A/628A/648A 9.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RB3/CCP1. An event is defined as: • Every falling edge • Every rising edge • Every 4th rising edge • Every 16th rising edge An event is selected by control bits CCP1M<3:0> ...
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... CCP1X x = unknown unchanged unimplemented read as ‘0’. Shaded cells are not used by Capture and Timer1. Legend: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 9.2.4 SPECIAL EVENT TRIGGER In this mode (CCP1M<3:0>=1011), an internal hard- ware trigger is generated, which may be used to initiate an action. See Register 9-1. ...
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... PIC16F627A/628A/648A 9.3 PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTB data latch, the TRISB<3> bit must be cleared to make the CCP1 pin an output. Clearing the CCP1CON register will force ...
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... CCP1CON — — unknown unchanged unimplemented read as ‘0’. Shaded cells are not used by PWM and Timer2. Legend: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Maximum PWM resolution (bits) for a given PWM frequency: PWM Resolution If the PWM duty cycle value is longer than ...
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... PIC16F627A/628A/648A NOTES: DS40044G-page 62 © 2009 Microchip Technology Inc. ...
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... Figure 10-1 shows the comparator modes and CM<2:0> bit settings Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC16F627A/628A/648A The CMCON register, shown in Register 10-1, controls the comparator input and output multiplexers. A block two analog diagram of the comparator is shown in Figure 10-1. ...
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... PIC16F627A/628A/648A 10.1 Comparator Configuration There are eight modes of operation for the comparators. The CMCON register is used to select the mode. Figure 10-1 shows the eight possible modes. The TRISA register controls the data direction of the comparator pins for each mode. FIGURE 10-1: ...
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... Comparator Reference An external or internal reference signal may be used depending on the comparator Operating mode. The analog signal that is present compared to the IN signal and the digital output of the comparator IN is adjusted accordingly (Figure 10-2). © 2009 Microchip Technology Inc. PIC16F627A/628A/648A FIGURE 10- ...
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... PIC16F627A/628A/648A 10.5 Comparator Outputs The comparator outputs are read through the CMCON register. These bits are read-only. The comparator outputs may also be directly output to the RA3 and RA4 I/O pins. When the CM<2:0> = 110 or 001, multiplexors in the output path of the RA3 and RA4/T0CK1/CMP2 ...
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... Clear flag bit CMIF. A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 10.7 Comparator Operation During Sleep When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional if enabled ...
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... PIC16F627A/628A/648A FIGURE 10-4: ANALOG INPUT MODE R < PIN Legend PIN LEAKAGE TABLE 10-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Address Name Bit 7 Bit 6 1Fh CMCON C2OUT C1OUT 0Bh, 8Bh, INTCON GIE PEIE 10Bh, 18Bh 0Ch PIR1 EEIF CMIF 8Ch PIE1 EEIE CMIE ...
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... REF When VRR = 1: V When VRR = 0: V Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC16F627A/628A/648A The equations used to calculate the output of the Voltage Reference module are as follows: if VRR = 1: if VRR = 0: V REF The setting time of the Voltage Reference module must be considered when changing the V (Table 17-3) ...
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... PIC16F627A/628A/648A FIGURE 11-1: VOLTAGE REFERENCE BLOCK DIAGRAM V DD VREN 8R V REF R is defined in Table 17-3. Note: EXAMPLE 11-1: VOLTAGE REFERENCE CONFIGURATION MOVLW 0x02 ;4 Inputs Muxed MOVWF CMCON ;to 2 comps. BSF STATUS,RP0 ;go to Bank 1 MOVLW 0x07 ;RA3-RA0 are MOVWF TRISA ;outputs MOVLW 0xA6 ...
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... VREN VROE 1Fh CMCON C2OUT C1OUT 85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 - = Unimplemented, read as ‘0’. Legend: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Op Amp RA2 + Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 VRR — VR3 ...
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... PIC16F627A/628A/648A NOTES: DS40044G-page 72 © 2009 Microchip Technology Inc. ...
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... TX9D: 9th bit of transmit data. Can be parity bit. Note 1: SREN/CREN overrides TXEN in SYNC mode. Legend Readable bit -n = Value at POR © 2009 Microchip Technology Inc. PIC16F627A/628A/648A The USART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous • Synchronous Bit SPEN (RCSTA<7>) and bits TRISB<2:1> have to be ...
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... PIC16F627A/628A/648A REGISTER 12-2: RCSTA – RECEIVE STATUS AND CONTROL REGISTER (ADDRESS: 18h) R/W-0 R/W-0 SPEN bit 7 bit 7 SPEN: Serial Port Enable bit (Configures RB1/RX/DT and RB2/TX/CK pins as serial port pins when bits TRISB<2:1> are set Serial port enabled 0 = Serial port disabled ...
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... SPBRG Baud Rate Generator Register x = unknown unimplemented read as ‘0’. Shaded cells are not used for the BRG. Legend: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A EQUATION 12-1: Desired Baud Rate Calculated Baud Rate , the nearest (Calculated Baud Rate - Desired Baud Rate) ...
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... PIC16F627A/628A/648A TABLE 12-3: BAUD RATES FOR SYNCHRONOUS MODE MHz SPBRG OSC BAUD RATE (K) KBAUD ERROR (decimal) 0.3 NA — 1.2 NA — 2.4 NA — 9.6 NA — 19.2 19.53 +1.73% 76.8 76.92 +0.16% 96 96.15 +0.16% 300 294.1 -1.96 500 500 0 HIGH 5000 — LOW 19.53 — ...
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... NA — — 300 NA — 500 NA — HIGH 55.93 — LOW 0.2185 — © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 16 MHz SPBRG value value KBAUD ERROR (decimal) — NA — — 255 1.202 +0.16% 207 129 2.404 +0.16% 103 32 9.615 +0 ...
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... PIC16F627A/628A/648A TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = MHz SPBRG OSC BAUD RATE (K) KBAUD ERROR (decimal) 9600 9.615 +0.16% 19200 19.230 +0.16% 38400 37.878 -1.36% 57600 56.818 -1.36% 115200 113.636 -1.36% 250000 250 0 625000 625 0 1250000 1250 7.16 MHz SPBRG ...
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... Flag bit TXIF is set when enable bit TXEN is set. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Transmission is enabled by setting enable bit TXEN (TXSTA<5>). The actual transmission will not occur until the TXREG register has been loaded with data and the Baud Rate Generator (BRG) has produced a shift clock (Figure 12-1) ...
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... PIC16F627A/628A/648A FIGURE 12-1: USART TRANSMIT BLOCK DIAGRAM TXIF TXIE Interrupt TXEN Baud Rate CLK SPBRG Baud Rate Generator Follow these steps when setting up an Asynchronous Transmission: 1. TRISB<1> and TRISB<2> should both be set to ‘1’ to configure the RB1/RX/DT and RB2/TX/CK pins as inputs. Output drive, when required, is controlled by the peripheral circuitry ...
Page 81
... TXSTA CSRC TX9 99h SPBRG Baud Rate Generator Register x = unknown unimplemented locations read as ‘0’. Legend: Shaded cells are not used for Asynchronous Transmission. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A bit 0 bit 1 Word 1 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RCIF TXIF — ...
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... PIC16F627A/628A/648A 12.2.2 USART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 12-4. The data is received on the RB1/RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate ...
Page 83
... Buffer) because ADEN was updated after an address match, and was cleared to a ‘0’, so the contents of the Receive Shift Register (RSR) are read into the Receive Buffer regardless of the value of bit 8. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Start Stop bit 8 ...
Page 84
... PIC16F627A/628A/648A Follow these steps when setting up an Asynchronous Reception: 1. TRISB<1> and TRISB<2> should both be set to ‘1’ to configure the RB1/RX/DT and RB2/TX/CK pins as inputs. Output drive, when required, is controlled by the peripheral circuitry. 2. Initialize the SPBRG register for the appropriate baud rate high-speed baud rate is desired, set bit BRGH. (Section 12.1 “ ...
Page 85
... Shaded cells are not used for asynchronous Legend: reception. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A The ADEN bit will only take effect when the receiver is configured in 9-bit mode (RX9 = 1). When ADEN is disabled (= 0), all data bytes are received and the 9th bit can be used as the parity bit ...
Page 86
... PIC16F627A/628A/648A 12.4 USART Synchronous Master Mode In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition enable bit SPEN (RCSTA<7>) is set in order to configure the RB2/TX/CK and RB1/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively ...
Page 87
... Note: FIGURE 12-9: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RB1/RX/DT pin RB2/TX/CK pin Write to TXREG Reg TXIF bit TRMT bit TXEN bit © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 ADEN FERR OERR TXIE — ...
Page 88
... PIC16F627A/628A/648A 12.4.2 USART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either enable (RCSTA<5>) or enable bit CREN (RCSTA<4>). Data is sampled on the RB1/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, then only a single word is received. If enable bit CREN is set, the recep- tion is continuous until CREN is cleared ...
Page 89
... If enable bit TXIE is set, the interrupt will wake the chip from Sleep and if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). © 2009 Microchip Technology Inc. PIC16F627A/628A/648A bit 2 bit 3 bit 4 bit 5 Follow these steps when setting up a Synchronous Slave Transmission: 1 ...
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... PIC16F627A/628A/648A 12.5.2 USART SYNCHRONOUS SLAVE RECEPTION The operation of the Synchronous Master and Slave modes is identical except in the case of the Sleep mode. Also, bit SREN is a “don’t care” in Slave mode. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during Sleep ...
Page 91
... EEADR EEDATA holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. PIC16F627A/628A devices have 128 bytes of data EEPROM with an address range from 0h to 7Fh. The PIC16F648A device has 256 bytes of data EEPROM with an address range from 0h to FFh. ...
Page 92
... The PIC16F648A EEADR register addresses 256 bytes of data EEPROM. All eight bits in the register (EEADR<7:0>) are required. The PIC16F627A/628A EEADR register addresses only the first 128 bytes of data EEPROM so only seven of the eight bits in the register (EEADR<6:0>) are required. The upper bit is address decoded. This means that this bit should always be ‘ ...
Page 93
... WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit ...
Page 94
... PIC16F627A/628A/648A 13.7 Using the Data EEPROM The data EEPROM is a high endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while ...
Page 95
... EECON2 EEPROM Control Register unknown unchanged unimplemented read as ‘0’ value depends upon condition. Legend: Shaded cells are not used by data EEPROM. EECON2 is not a physical register. Note 1: © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 — — WRERR ...
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... PIC16F627A/628A/648A NOTES: DS40044G-page 96 © 2009 Microchip Technology Inc. ...
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... Sleep 10. Code protection 11. ID Locations 12. In-Circuit Serial Programming™ (ICSP™) The PIC16F627A/628A/648A has a Watchdog Timer which is controlled by configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable ...
Page 98
... Flash program memory needs to be bulk erased to set the CP bit, turning the code protection off. See “PIC16F627A/628A/648A EEPROM Memory Programming Specification” (DS41196) for details. The entire data EEPROM needs to be bulk erased to set the CPD bit, turning the code protection off. See “PIC16F627A/ 3: 628A/648A EEPROM Memory Programming Specification” ...
Page 99
... Oscillator Configurations 14.2.1 OSCILLATOR TYPES The PIC16F627A/628A/648A can be operated in eight different oscillator options. The user can program three configuration bits (FOSC2 through FOSC0) to select one of these eight modes: • LP Low Power Crystal • XT Crystal/Resonator • HS High Speed Crystal/Resonator • RC External Resistor/Capacitor (2 modes) • ...
Page 100
... EXTERNAL CLOCK IN For applications where a clock is already available elsewhere, users may directly drive the PIC16F627A/ 628A/648A provided that this external clock source meets the AC/DC timing requirements listed in Section 17.6 “Timing Diagrams and Specifications”. Figure 14-4 below shows how an external clock circuit should be configured ...
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... SPECIAL FEATURE: DUAL-SPEED OSCILLATOR MODES A software programmable dual-speed oscillator mode is provided when the PIC16F627A/628A/648A is configured in the INTOSC oscillator mode. This feature allows users to dynamically toggle the oscillator speed between 4 MHz and 48 kHz nominal in the INTOSC mode. Applications that require low-current power ...
Page 102
... PIC16F627A/628A/648A FIGURE 14-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset Schmitt Trigger Input MCLR/ Sleep V Pin PP WDT WDT Module Time-out Reset V Rise DD Detect Power-on Reset V DD Brown-out Reset BOREN OST/PWRT OST 10-bit Ripple-counter OSC1/ CLKIN Pin PWRT (1) On-chip 10-bit Ripple-counter OSC This is a separate oscillator from the INTOSC/RC oscillator ...
Page 103
... The OST time out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from Sleep. See Table 17-7. 14.4.4 BROWN-OUT RESET (BOR) The PIC16F627A/628A/648A have on-chip BOR circuitry. A configuration bit, BOREN, can disable (if parameters clear/programmed) or enable (if set) the BOR circuitry ...
Page 104
... Then bringing MCLR high will begin execution immediately (see Figure 14-11). This is useful for testing purposes or to synchronize more than one PIC16F627A/628A/ 648A device operating in parallel. Table 14-6 shows the Reset conditions for some special registers, while Table 14-7 shows the Reset conditions for all the registers ...
Page 105
... Legend: Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h) after execution © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 ...
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... PIC16F627A/628A/648A TABLE 14-7: INITIALIZATION CONDITION FOR REGISTERS Register Address Power-on Reset W — xxxx xxxx INDF 00h, 80h, — 100h, 180h TMR0 01h, 101h xxxx xxxx PCL 02h, 82h, 0000 0000 102h, 182h STATUS 03h, 83h, 0001 1xxx 103h, 183h FSR 04h, 84h, ...
Page 107
... Internal POR PWRT Time Out OST Time Out Internal Reset FIGURE 14-10: TIME OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR Internal POR PWRT Time Out OST Time Out Internal Reset © 2009 Microchip Technology Inc. PIC16F627A/628A/648A T PWRT T OST T PWRT T OST DD T PWRT T OST ...
Page 108
... Transistor Q1 turns off when V 2: Internal Brown-out Reset should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor. pin break- DD EXTERNAL BROWN-OUT PROTECTION CIRCUIT MCLR 40k PIC16F627A/628A/648A is below a certain level such that 0 0 © 2009 Microchip Technology Inc. ...
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... Interrupts The PIC16F627A/628A/648A has 10 sources of interrupt: • External Interrupt RB0/INT • TMR0 Overflow Interrupt • PORTB Change Interrupts (pins RB<7:4>) • Comparator Interrupt • USART Interrupt TX • USART Interrupt RX • CCP Interrupt • TMR1 Overflow Interrupt • TMR2 Match Interrupt • ...
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... PIC16F627A/628A/648A 14.5.1 RB0/INT INTERRUPT External interrupt on the RB0/INT pin is edge triggered; either rising if INTEDG bit (OPTION<6>) is set, or falling, if INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>). The INTF bit must be cleared in software in the interrupt service routine before re-enabling this interrupt ...
Page 111
... W, sets bank to original ;state MOVWF STATUS ;move W into STATUS ;register SWAPF W_TEMP,F ;swap W_TEMP SWAPF W_TEMP,W ;swap W_TEMP into W © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 T0IE INTE RBIE T0IF INTF RCIF TXIF — CCP1IF TMR2IF TMR1IF ...
Page 112
... PIC16F627A/628A/648A FIGURE 14-16: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure 6-1) Watchdog Timer WDT Enable Bit T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register. Note: TABLE 14-9: SUMMARY OF WATCHDOG TIMER REGISTERS Address Name Bit 7 Bit 6 2007h CONFIG LVP ...
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... CLKOUT is not available in these Oscillator modes, but shown here for timing reference. 14.9 Code Protection With the Code-Protect bit is cleared (Code-Protect enabled), the contents of the program memory locations are read out as ‘0’. See “PIC16F627A/628A/ 648A EEPROM Memory Programming Specification” (DS41196) for details. Only a Bulk Erase function can set the CP Note: and CPD bits by turning off the code protection ...
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... PIC16F627A/628A/648A 14.11 In-Circuit Serial Programming™ (ICSP™) The PIC16F627A/628A/648A microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to ...
Page 115
... PIC16F648A-ICD device is used with MPLAB ICD 2 to provide separate clock, data and MCLR pins and frees all normally available pins to the user. Debugging of all three versions of the PIC16F627A/628A/648A is supported by the PIC16F648A-ICD. This special ICD device is mounted on the top of a header and its signals are routed to the MPLAB ICD 2 connector. On the bottom of the header is an 18-pin socket that plugs into the user’ ...
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... PIC16F627A/628A/648A NOTES: DS40044G-page 116 © 2009 Microchip Technology Inc. ...
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... INSTRUCTION SET SUMMARY Each PIC16F627A/628A/648A instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16F627A/628A/648A instruction set summary in Table 15-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 15-1 shows the opcode field descriptions. For byte-oriented instructions, ‘ ...
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... PIC16F627A/628A/648A TABLE 15-2: PIC16F627A/628A/648A INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS f, d Add W and f ADDWF f, d AND W with f ANDWF f Clear f CLRF — Clear W CLRW f, d Complement f COMF f, d Decrement f DECF f, d Decrement f, Skip if 0 DECFSZ f, d Increment f INCF f, d Increment f, Skip if 0 ...
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... Cycles: 1 Example ADDWF REG1, 0 Before Instruction W = 0x17 REG1 = 0xC2 After Instruction W = 0xD9 REG1 = 0xC2 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A ANDLW k Syntax: Operands: Operation: Status Affected: kkkk kkkk Encoding: Description: Words: Cycles: Example ANDWF Syntax: f,d Operands: Operation: Status Affected: Encoding: ...
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... PIC16F627A/628A/648A BCF Bit Clear f Syntax: [ label ] BCF f,b 0 ≤ f ≤ 127 Operands: 0 ≤ b ≤ → (f<b>) Operation: Status Affected: None Encoding: 01 00bb Description: Bit ‘b’ in register ‘f’ is cleared. Words: 1 Cycles: 1 Example BCF REG1, 7 Before Instruction REG1 = 0xC7 After Instruction ...
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... FALSE GOTO TRUE • • • Before Instruction PC = address HERE After Instruction if FLAG<1> address FALSE if FLAG<1> address TRUE © 2009 Microchip Technology Inc. PIC16F627A/628A/648A CALL Syntax: Operands: Operation: Status Affected: bfff ffff Encoding: Description: Words: Cycles: REG1 Example PROCESS_CODE CLRF Syntax: ...
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... PIC16F627A/628A/648A CLRW Clear W Syntax: [ label ] CLRW Operands: None 00h → (W) Operation: 1 → Z Status Affected: Z Encoding: 00 0001 Description: W register is cleared. Zero bit (Z) is set. Words: 1 Cycles: 1 Example CLRW Before Instruction W = 0x5A After Instruction W = 0x00 CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None 00h → ...
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... Before Instruction PC = address After Instruction REG1 = REG1 - 1 if REG1 = address CONTINUE if REG1 ≠ address HERE+1 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A GOTO Syntax: Operands: Operation: skip if result = Status Affected: Encoding: dfff ffff Description: Words: Cycles: Example REG1, 1 LOOP HERE ...
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... PIC16F627A/628A/648A INCF Increment f Syntax: [ label ] INCF f,d 0 ≤ f ≤ 127 Operands: d ∈ [0,1] ( → (dest) Operation: Status Affected: Z Encoding: 00 1010 Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘ ...
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... Words: 1 Cycles: 1 Example IORWF REG1, 0 Before Instruction REG1 = 0x13 W = 0x91 After Instruction REG1 = 0x13 W = 0x93 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A MOVLW Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: Words: Cycles: Example MOVF f,d Syntax: Operands: Operation: Status Affected: ...
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... PIC16F627A/628A/648A MOVWF Move Syntax: [ label ] MOVWF 0 ≤ f ≤ 127 Operands: (W) → (f) Operation: Status Affected: None Encoding: 00 0000 Description: Move data from W register to register ‘f’. Words: 1 Cycles: 1 Example MOVWF REG1 Before Instruction REG1 = 0xFF W = 0x4F After Instruction REG1 = 0x4F W = 0x4F NOP ...
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... POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. Words: 1 Cycles: 2 Example RETURN After Interrupt PC = TOS © 2009 Microchip Technology Inc. PIC16F627A/628A/648A RLF Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: Words: Cycles: Example ...
Page 128
... PIC16F627A/628A/648A RRF Rotate Right f through Carry Syntax: [ label ] RRF f,d 0 ≤ f ≤ 127 Operands: d ∈ [0,1] Operation: See description below Status Affected: C Encoding: 00 1100 Description: The contents of register ‘f’ are rotated one bit to the right through the Carry Flag. If ‘d’ is ‘ ...
Page 129
... result is zero Example 3: Before Instruction REG1 = After Instruction REG1 = 0xFF result is negative © 2009 Microchip Technology Inc. PIC16F627A/628A/648A SWAPF Syntax: Operands: Operation: Status Affected: Encoding: dfff ffff Description: Words: Cycles: Example TRIS Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: ...
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... PIC16F627A/628A/648A XORLW Exclusive OR Literal with W Syntax: [ label ] XORLW k 0 ≤ k ≤ 255 Operands: (W) .XOR. k → (W) Operation: Status Affected: Z Encoding: 11 1010 Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. Words: 1 Cycles: ...
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... Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 16.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...
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... PIC16F627A/628A/648A 16.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal control- lers. These compilers provide powerful integration capabilities, superior code optimization and ease of use ...
Page 133
... Microchip Technology Inc. PIC16F627A/628A/648A 16.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- chip's most cost effective high-speed hardware ...
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... PIC16F627A/628A/648A 16.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use inter- face for programming and debugging Microchip’s Flash families of microcontrollers. The ® Windows programming interface supports baseline (PIC10F, PIC12F5xx, ...
Page 135
... Exposure to maximum rating conditions for extended periods may affect device reliability. Voltage spikes below V Note: SS Thus, a series resistor of 50-100 pulling this pin directly to V © 2009 Microchip Technology Inc. PIC16F627A/628A/648A ............................................................................................-0.3 to +14V SS ....................................................................................-0. )..................................................................................................................... ± )............................................................................................................... ± – ...
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... PIC16F627A/628A/648A PIC16F627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C FIGURE 17-1: 6.0 5.5 5.0 4 (VOLTS) 4.0 3.5 3.0 2.5 0 The shaded region indicates the permissible combinations of voltage and frequency. Note: PIC16LF627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +85°C FIGURE 17-2: 6.0 5.5 5 ...
Page 137
... DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended) PIC16LF627A/628A/648A (Industrial) PIC16LF627A/628A/648A (Industrial) PIC16F627A/628A/648A (Industrial, Extended) Param Sym Characteristic/Device No Supply Voltage D001 PIC16LF627A/628A/648A PIC16F627A/628A/648A D002 V DR RAM Data Retention (1) Voltage D003 V POR V Start Voltage DD to ensure Power-on Reset D004 S VDD V Rise Rate DD to ensure Power-on Reset ...
Page 138
... PIC16F627A/628A/648A 17.2 DC Characteristics: PIC16F627A/628A/648A (Industrial) PIC16LF627A/628A/648A (Industrial) DC CHARACTERISTICS Param LF and F Device No. Characteristics Supply Voltage ( D001 LF/F Power-down Base Current ( D020 LF/F (1) Peripheral Module Current (ΔI ) MOD LF D021 LF/F LF/F D022 LF D023 LF/F LF D024 LF/F LF D025 LF/F Supply Current ( D010 LF/F LF D011 ...
Page 139
... DC Characteristics: PIC16F627A/628A/648A (Extended) DC CHARACTERISTICS Param Device Characteristics No. Supply Voltage ( D001 — Power-down Base Current ( — D020E (1) Peripheral Module Current (ΔI ) MOD — D021E — D022E — D023E — D024E — D025E Supply Current ( — D010E — D011E — D012E — ...
Page 140
... These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested oscillator configuration, the OSC1 pin is a Schmitt Trigger input not recommended that the PIC16F627A/628A/648A Note 1: be driven with external clock in RC mode ...
Page 141
... TABLE 17-1: DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended) DC CHARACTERISTICS Parameter Sym Characteristic No. Data EEPROM Memory D120 E Endurance D D120A E Endurance D D121 V V for read/write DRW DD D122 T Erase/Write cycle time DEW D123 T Characteristic Retention RETD D124 T Number of Total Erase/Write REF Cycles before Refresh Program Flash Memory ...
Page 142
... PIC16F627A/628A/648A TABLE 17-2: COMPARATOR SPECIFICATIONS Operating Conditions: 2.0V < V Param Characteristics No. D300 Input Offset Voltage D301 Input Common Mode Voltage D302 Common Mode Rejection Ratio (1) D303 Response Time D304 Comparator Mode Change to Output Valid * These parameters are characterized but not tested. ...
Page 143
... Uppercase letters and their meanings Fall H High I Invalid (High-impedance) L Low FIGURE 17-3: LOAD CONDITIONS Load Condition 1 Pin R = 464Ω for all pins except OSC2 for OSC2 output © 2009 Microchip Technology Inc. PIC16F627A/628A/648A T osc Load Condition Pin V SS Time OSC1 T0CKI Period Rise ...
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... PIC16F627A/628A/648A 17.6 Timing Diagrams and Specifications FIGURE 17-4: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT TABLE 17-4: EXTERNAL CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic No. F External CLKIN Frequency OSC Oscillator Frequency 1 T External CLKIN Period OSC Oscillator Period 2 T Instruction Cycle Time CY 3 TosL, ...
Page 145
... Legend: TBD = To Be Determined. * Characterized but not tested. FIGURE 17-5: CLKOUT AND I/O TIMING Q4 OSC1 CLKOUT I/O Pin (input) I/O Pin Old Value (output) © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Min Typ Max Units — 4 — MHz 3.96 4 4.04 MHz V MHz 2.0V ≤ ...
Page 146
... PIC16F627A/628A/648A TABLE 17-6: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym Characteristic No OSC1↑ to CLKOUT↓ 10A OSC1↑ to CLKOUT↑ 11A CLKOUT rise time CK 12A CLKOUT fall time CK 13A CLKOUT ↓ to Port out valid Port in valid before CLKOUT ↑ Port in hold after CLKOUT ↑ ...
Page 147
... Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI/CMP2 RB6/T1OSO/T1CKI/PGC TMR0 OR TMR1 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A V BOR 35 Min Typ† Max Units 2000 — ...
Page 148
... PIC16F627A/628A/648A TABLE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic No T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period T1CKI High Synchronous, No Prescaler T Time Synchronous, with Prescaler Asynchronous PIC16F62XA T1CKI Low Synchronous, No Prescaler T Time Synchronous, with Prescaler Asynchronous PIC16F62XA ...
Page 149
... F CCP output fall time CC * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Min 0.5T ...
Page 150
... PIC16F627A/628A/648A NOTES: DS40044G-page 150 © 2009 Microchip Technology Inc. ...
Page 151
... FIGURE 18-1: TYPICAL BASELINE I 160 140 120 100 2.0 2.5 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A ° ° vs -40°C 0°C +25°C 3.0 3.5 4.0 V ...
Page 152
... PIC16F627A/628A/648A FIGURE 18-2: TYPICAL BASELINE I 300 280 260 240 220 200 180 160 140 120 100 2.0 2.5 FIGURE 18-3: TYPICAL BASELINE CURRENT I 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 2.0 2.5 3.0 DS40044G-page 152 ° vs +85°C 3.0 3.5 4 ...
Page 153
... FIGURE 18-4: TYPICAL BOR 4.5 4.6 4.7 FIGURE 18-5: TYPICAL SINGLE COMPARATOR 2.5 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A vs 4.8 4.9 5.0 5.1 5.2 V (Volts 3.5 4 4.5 V (Volts) DD 125°C 85°C 25°C 0°C -40°C 5.3 5.4 5.5 125°C 85°C 25° ...
Page 154
... PIC16F627A/628A/648A FIGURE 18-6: TYPICAL V REF 100 2.0 2.5 3.0 FIGURE 18-7: TYPICAL WDT 2.0 2.5 3.0 DS40044G-page 154 I vs 3.5 4.0 4.5 V (Volts 3.5 4.0 4.5 V (Volts) DD 125°C 85°C 25°C 0°C -40°C 5.0 5.5 125°C 85°C 25°C 0°C -40° ...
Page 155
... FIGURE 18-8: AVERAGE 2.5 FIGURE 18-9: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE VOLTS DD 5.0% 4.0% 3.0% 2.0% 1.0% 0.0% -1.0% -2.0% -3.0% -4.0% -5.0% -40 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A _TIMER1 3 3.5 4 4 Temperature (ºC) -40C 0C 25C 85C 125 5 5.5 125 DS40044G-page 155 ...
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... PIC16F627A/628A/648A FIGURE 18-10: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE VOLTS DD 5.0% 4.0% 3.0% 2.0% 1.0% 0.0% -1.0% -2.0% -3.0% -4.0% -5.0% -40 FIGURE 18-11: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE VOLTS DD 5.0% 4.0% 3.0% 2.0% 1.0% 0.0% -1.0% -2.0% -3.0% -4.0% -5.0% -40 DS40044G-page 156 ...
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... FIGURE 18-13: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. V -40°C TO 85°C 5.0% 4.0% 3.0% 2.0% 1.0% 0.0% -1.0% -2.0% -3.0% -4.0% -5.0% 2 2.5 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A 3 3.5 4 4 3.5 4 4 25°C – 4 MHz MODE DD 5 5.5 TEMPERATURE = ...
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... PIC16F627A/628A/648A FIGURE 18-14: INTERNAL OSCILLATOR I 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 2 2.5 FIGURE 18-15: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. V MODE 2.5 DS40044G-page 158 vs. V – 4 MHz MODE Avg - 3.5 4 4 5.5 AT 25°C – SLOW DD 4.5 5 5.5 © 2009 Microchip Technology Inc. ...
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... FIGURE 18-17: SUPPLY CURRENT (I 500 450 400 350 300 250 200 150 100 2.0 2.5 3.0 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A vs. V – SLOW MODE Avg - 3.5 4 4.5 V ( MHz (XT OSCILLATOR MODE OSC 3.5 4.0 4.5 ...
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... PIC16F627A/628A/648A FIGURE 18-18: SUPPLY CURRENT (I 1000 900 800 700 600 500 400 300 200 2.0 2.5 FIGURE 18-19: SUPPLY CURRENT (I 4.0 3.5 3.0 2.5 2.0 4.5 4.6 4.7 4.8 DS40044G-page 160 vs MHz (XT OSCILLATOR MODE OSC 3.0 3.5 4.0 4.5 V (Volts vs MHz (HS OSCILLATOR MODE) ...
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... FIGURE 18-20: TYPICAL WDT PERIOD vs 2.5 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A (-40°C TO +125°C) DD WDT Time-out 3 3.5 4 4.5 V ( 125 5 5.5 DS40044G-page 161 ...
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... PIC16F627A/628A/648A NOTES: DS40044G-page 162 © 2009 Microchip Technology Inc. ...
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... Note : In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A Example PIC16F627A -I 0410017 Example PIC16F628A -E/SO ...
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... PIC16F627A/628A/648A N NOTE DS40044G-page 164 © 2009 Microchip Technology Inc. ...
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... D N NOTE © 2009 Microchip Technology Inc. PIC16F627A/628A/648A α φ A2 β DS40044G-page 165 ...
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... PIC16F627A/628A/648A DS40044G-page 166 © 2009 Microchip Technology Inc. ...
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... D N NOTE © 2009 Microchip Technology Inc. PIC16F627A/628A/648A φ L DS40044G-page 167 ...
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... PIC16F627A/628A/648A D TOP VIEW A3 DS40044G-page 168 EXPOSED PAD NOTE 1 BOTTOM VIEW © 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC16F627A/628A/648A DS40044G-page 169 ...
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... PIC16F627A/628A/648A NOTES: DS40044G-page 170 © 2009 Microchip Technology Inc. ...
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... Development Support Section; Revised Product ID System. Revision G (10/2009) Corrected 28-lead QFN Package in Section 19.1. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A APPENDIX B: The differences between the PIC16F627A/628A/648A devices listed in this data sheet are shown in Table B-1. TABLE B-1: DEVICE DIFFERENCES Device Program PIC16F627A ...
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... Dual-Speed Oscillator mode worked in both the INTRC and ER oscillator modes. DS40044G-page 172 APPENDIX D: as from a This discusses some of the issues in migrating from other PIC MCU devices to the PIC16F627A/628A/ 648A family of devices. D.1 PIC16C62X/CE62X to PIC16F627A/ 628A/648A Migration See Microchip (www.microchip.com). ...
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... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2009 Microchip Technology Inc. PIC16F627A/628A/648A CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC16F627A/628A/648A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...
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... PWM Mode. See PWM Timer Resources......................................................... 57 CCP1CON Register ............................................................ 57 CCP1M Bits ................................................................ 57 CCP1X:CCP1Y Bits .................................................... 57 CCP2CON Register CCP2M<3:2> Bits ....................................................... 57 © 2009 Microchip Technology Inc. PIC16F627A/628A/648A CCP2X:CCP2Y Bits.................................................... 57 Clocking Scheme/Instruction Cycle .................................... 15 CLRF Instruction............................................................... 121 CLRW Instruction.............................................................. 122 CLRWDT Instruction......................................................... 122 CMCON Register................................................................ 63 Code Examples Data EEPROM Refresh Routine ................................ 94 Code Protection ...
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... PIC16F627A/628A/648A I I/O Ports .............................................................................. 33 Bidirectional ................................................................ 46 Block Diagrams RB0/INT Pin ........................................................ 38 RB1/RX/DT Pin ................................................... 39 RB2/TX/CK Pin ................................................... 39 RB3/CCP1 Pin .................................................... 40 RB4/PGM Pin...................................................... 41 RB5 Pin............................................................... 42 RB6/T1OSO/T1CKI Pin ...................................... 43 RB7/T1OSI Pin ................................................... 44 PORTA........................................................................ 33 PORTB........................................................................ 38 Programming Considerations ..................................... 46 Successive Operations ............................................... 46 TRISA ......................................................................... 33 TRISB ......................................................................... 38 ID Locations ...................................................................... 113 INCF Instruction ................................................................ 124 INCFSZ Instruction............................................................ 124 In-Circuit Serial Programming™ ....................................... 114 Indirect Addressing, INDF and FSR Registers ...
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... Registers CCP1CON (CCP Operation)....................................... 57 CMCON (Comparator Configuration).......................... 63 CONFIG (Configuration Word).................................... 98 EECON1 (EEPROM Control Register 1) .................... 92 INTCON (Interrupt Control)......................................... 26 Maps PIC16F627A ................................................. 18, 19 PIC16F628A ................................................. 18, 19 OPTION_REG (Option) .............................................. 25 PCON (Power Control) ............................................... 29 PIE1 (Peripheral Interrupt Enable 1)........................... 27 PIR1 (Peripheral Interrupt Register 1) ........................ 28 Status.......................................................................... 24 T1CON Timer1 Control).............................................. 50 T2CON Timer2 Control) ...
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... PIC16F627A/628A/648A Synchronous Slave Transmit ...................................... 89 V Voltage Reference Configuration............................................................... 69 Voltage Reference Module ......................................... 69 W Watchdog Timer (WDT) .................................................... 111 WWW Address.................................................................. 173 WWW, On-Line Support........................................................ 5 X XORLW Instruction ........................................................... 130 XORWF Instruction ........................................................... 130 DS40044G-page 178 © 2009 Microchip Technology Inc. ...
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... Package SOIC (Gull Wing, 7.50 mm body SSOP (5. QFN (28 Lead) © 2009 Microchip Technology Inc. PIC16F627A/628A/648A XXX Examples: a) PIC16F627A - E/P 301 = Extended Pattern Temp., PDIP package, 20 MHz, normal V its, QTP pattern #301. range 3. PIC16LF627A - I/SO = Industrial Temp., SOIC package, 20 MHz, extended V range 3.0V to 5.5V DD limits ...
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... Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2009 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...