PIC18F26K20-E/SO Microchip Technology, PIC18F26K20-E/SO Datasheet - Page 402

• Manufacturer Part Number: PIC18F26K20-E/SO
• Description: IC PIC MCU FLASH 16KX16 28-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26K20-E/SO

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: CCP/ECCP/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164303 - MODULE SKT FOR PM3 64TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2XK20/4XK20
FIGURE 26-22:
TABLE 26-25: A/D CONVERSION REQUIREMENTS
DS41303G-page 402
130
131
132
135
136
Legend: TBD = To Be Determined
Note 1:
Param
No.
Note 1:
2:
3:
4:
A/D DATA
SAMPLE
A/D CLK
T
T
T
T
T
ADRES
Symbol
AD
CNV
ACQ
SWC
BSF ADCON0, GO
DIS
ADIF
The time of the A/D clock period is dependent on the device frequency and the T
ADRES register may be read on the following T
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
.
On the following cycle of the device clock.
GO
2:
Q4
If the A/D clock source is selected as RC, a time of T
This allows the SLEEP instruction to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
A/D Clock Period
Conversion Time
(not including acquisition time) (Note 2)
Acquisition Time (Note 3)
Switching Time from Convert  Sample
Discharge Time
132
A/D CONVERSION TIMING
(Note 2)
Characteristic
DD
9
to V
SS
8
or V
OLD_DATA
SS
7
to V
.. .
SAMPLING STOPPED
DD
CY
). The source impedance (R
CY
is added before the A/D clock starts.
cycle.
. . .
131
130
Min
0.7
0.7
1.0
1.4
12
—
2
2
(Note 4)
25.0
4.0
Max
4.0
12
—
2
(1)
(1)
1
Units
T
T
s
s
s
s
AD
AD
S
 2010 Microchip Technology Inc.
) on the input channels is 50
0
T
-40C to +85C
T
+85C to +125C
FRC mode, V
V
OSC
OSC
DD
AD
= 3V, Rs = 50
based,
based,
clock divider.
NEW_DATA
DONE
Conditions
T
DD
CY
2.0V