PIC18F25J11-I/SP Microchip Technology, PIC18F25J11-I/SP Datasheet - Page 23
![IC PIC MCU FLASH 32KB 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F25J11-I/SP
Manufacturer Part Number
PIC18F25J11-I/SP
Description
IC PIC MCU FLASH 32KB 28-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
Specifications of PIC18F25J11-I/SP
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
16
Ram Memory Size
3.6875KB
Cpu Speed
48MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180023
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Details
TABLE 5-5:
TABLE 5-6:
© 2009 Microchip Technology Inc.
300000h CONFIG1L
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
300004h CONFIG3L DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 DSWDTEN DSBOREN
300005h CONFIG3H
300006h CONFIG4L
300007h CONFIG4H
3FFFFEh DEVID1
3FFFFFh DEVID2
Legend:
Note
WPFP<5:0>
WPDIS
DEV<2:0>
REV<4:0>
DEV<10:3>
Note 1: The Configuration bits can only be programmed indirectly by programming the Flash Configuration Word.
File Name
Bit Name
1:
2:
3:
4:
(5)
2: The Configuration bits are reset to ‘1’ only on V
3: These bits are not implemented in PIC18F46J11 family devices.
4: Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code
x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset states, the
configuration bytes maintain their previously programmed states.
The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it is
accidentally executed.
These bits are not implemented in PIC18F47J13 family devices.
This bit should always be maintained at ‘0’.
protection, perform an ICSP™ Bulk Erase operation.
PIC18F46J11 AND PIC18F46J50 FAMILY DEVICES: BIT DESCRIPTIONS (CONTINUED)
PIC18F47J13 AND PIC18F47J53 FAMILY DEVICES: CONFIGURATION BITS AND
DEVICE IDs
WPCFG
DEBUG
DEV10
DEV2
IESO
Bit 7
—
—
—
—
Configuration
(2)
(2)
(2)
(2)
CONFIG4H
CONFIG4L
DEVID1
DEVID1
DEVID2
Words
FCMEN
WPFP6
XINST
DEV1
DEV9
Bit 6
—
—
—
—
(2)
(2)
(2)
(2)
Write/Erase Protect Page Start/End Location bits
Used with WPEND bit to define which pages in Flash will be write/erase-protected.
Write Protect Disable bit
1 = WPFP<5:0>, WPEND and WPCFG bits ignored; all Flash memory may be erased or
0 = WPFP<5:0>, WPEND and WPCFG bits enabled; write/erase-protect active for the
Device ID bits
Used with the DEV<10:3> bits in the Device ID Register 2 to identify the part number.
Indicate the device revision.
Device ID bits
Used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number.
Revision ID bits
PIC18F2XJXX/4XJXX FAMILY
STVREN CFGPLLEN
CLKOEC SOSCSEL1 SOSCSEL0
WPFP5
DEV0
DEV8
written
selected region(s)
Bit 5
—
—
—
—
(2)
(2)
(2)
(2)
WPFP4
DD
REV4
DEV7
Bit 4
—
—
—
—
(2)
(2)
(2)
(2)
Reset; it is reloaded with the programmed value at any device Reset.
LS48MHZ
MSSPMSK
WDTPS3
PLLDIV2
WPFP3
REV3
DEV6
Bit 3
—
(4)
(3)
Description
WDTPS2
PLLDIV1
PLLSEL
FOSC2
WPFP2
REV2
DEV5
Bit 2
CP0
—
CPDIV1
WDTPS1
PLLDIV0
RTCOSC
ADCSEL
WPEND
FOSC1
WPFP1
REV1
DEV4
Bit 1
(3)
DSWDTOSC
CPDIV0
IOL1WAY
WDTPS0
WDTEN
FOSC0
WPFP0
WPDIS
REV0
DEV3
Bit 0
DS39687E-page 23
(3)
Unprogrammed
1111 1111
---- 1111
1111 1111
---- 1111
1111 1111
---- 1-11
xxxx xxxx
0101 10xx
111- 1111
---- 0111
Default/
Value
(1)