PIC18F26J50-I/SO Microchip Technology, PIC18F26J50-I/SO Datasheet - Page 265

• Manufacturer Part Number: PIC18F26J50-I/SO
• Description: IC PIC MCU FLASH 64K 2V 28-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26J50-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 16
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136, MA180024, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.1.6
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
Conversion. The ADC interrupt flag is the ADIF bit in
the PIR1 register. The ADC interrupt enable is the ADIE
bit in the PIE1 register. The ADIF bit must be cleared by
software.
TABLE 19-1:
19.1.7
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON2 register controls the output format.
Figure 19-2 shows the two output formats.
FIGURE 19-2:
© 2008 Microchip Technology Inc.
Legend: Shaded cells are outside of recommended range.
Note 1:
ADC Clock Source
Note:
F
F
F
2:
3:
4:
(ADFM = 0)
(ADFM = 1)
F
F
F
OSC
OSC
OSC
OSC
OSC
OSC
F
ADC Clock Period (T
RC
The F
These values violate the minimum required T
For faster conversion times, the selection of another clock source is recommended.
When the device frequency is greater than 1 MHz, the F
conversion will be performed during Sleep.
INTERRUPTS
The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
RESULT FORMATTING
/16
/32
/64
/2
/4
/8
RC
ADC CLOCK PERIOD (T
source has a typical T
10-BIT A/D CONVERSION RESULT FORMAT
MSB
bit 7
bit 7
Unimplemented: Read as ‘0’
ADCS<2:0>
AD
000
100
001
101
010
110
x11
)
ADRESH
AD
10-bit A/D Result
time of 1.7 μs.
AD
31.25 ns
) V
1-4 μs
62.5 ns
400 ns
250 ns
500 ns
64 MHz
Preliminary
1.0 μs
S
. DEVICE OPERATING FREQUENCIES
MSB
(1,4)
AD
(2)
(2)
(2)
(2)
(2)
time.
bit 0
bit 0
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
Interrupt Service Routine. Please see Section 19.1.6
“Interrupts” for more information.
PIC18F2XK20/4XK20
1-4 μs
RC
125 ns
250 ns
500 ns
Device Frequency (F
4.0 μs
16 MHz
1.0 μs
2.0 μs
clock source is only recommended if the
bit 7
bit 7
(1,4)
(3)
(2)
(2)
(2)
10-bit A/D Result
LSB
Unimplemented: Read as ‘0’
1-4 μs
16.0 μs
500 ns
4.0 μs
8.0 μs
4 MHz
1.0 μs
2.0 μs
ADRESL
OSC
(1,4)
(3)
(3)
(2)
(3)
)
DS41303D-page 263
1-4 μs
16.0 μs
32.0 μs
64.0 μs
4.0 μs
8.0 μs
1 MHz
2.0 μs
bit 0
LSB
bit 0
(1,4)
(3)
(3)
(3)
(3)
(3)