ATMEGA16A-AU Atmel, ATMEGA16A-AU Datasheet - Page 244

• Manufacturer Part Number: ATMEGA16A-AU
• Description: MCU AVR 16K FLASH 16MHZ 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

244
ATmega16A
As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3 when
the power supply is 5.0V and AREF is externally connected to V
The recommended values from
rithm in
“Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register
with the succeeding columns. The verification should be done on the data scanned out when
scanning in the data on the same row in the table.
Table 24-7.
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-
quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at
least five times the number of scan bits divided by the maximum hold time, t
Step
• In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when
• The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal
10
11
1
2
3
4
5
6
7
8
9
enabling the ADC. The user is advised to wait at least 200 ns after enabling the ADC before
controlling/observing any ADC signal, or perform a dummy conversion before using the first
result.
low (Sample mode).
Table
Actions
SAMPLE_
PRELOAD
EXTEST
Verify the
COMP bit
scanned
out to be 0
Verify the
COMP bit
scanned
out to be 1
24-7. Only the DAC and Port Pin values of the Scan-chain are shown. The column
Algorithm for Using the ADC
The lower limit is:
The upper limit is:
ADCEN
1
1
1
1
1
1
1
1
1
1
1
DAC
0x200
0x200
0x200
0x123
0x123
0x200
0x200
0x200
0x143
0x143
0x200
Table 24-6
1024 1,5V 0,95 5V
1024 1,5V 1,05 5V
MUXEN
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
⋅
are used unless other values are given in the algo-
⋅
⋅
⋅
HOLD
1
0
1
1
1
1
0
1
1
1
1
⁄
⁄
PRECH
=
=
291
1
1
1
1
0
1
1
1
1
0
1
323
CC
.
=
=
0x123
0x143
PA3.
Data
0
0
0
0
0
0
0
0
0
0
0
hold,max
PA3.
Control
0
0
0
0
0
0
0
0
0
0
0
8154B–AVR–07/09
.
PA3.
Pullup_
Enable
0
0
0
0
0
0
0
0
0
0
0