PIC24FJ32GB004-I/PT Microchip Technology, PIC24FJ32GB004-I/PT Datasheet - Page 5

• Manufacturer Part Number: PIC24FJ32GB004-I/PT
• Description: IC MCU 16BIT 32KB FLASH 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ32GB004-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (11K x 24)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM240001, MA240019, DM240002, DM240011, DV164033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9. Module: Triple (Enhanced) Comparator
10. Module: Core (Doze Mode)
 2010 Microchip Technology Inc.
When any of the internal band gap options (V
V
ence module as the comparator’s CV
the comparator may not generate an interrupt
when a preprogrammed event is detected.
The
described.
Work around
If it is necessary to use the internal band gap as
a reference, do the following:
1.
2.
Affected Silicon Revisions
Operations that immediately follow any manipu-
lations of the DOZE<2:0> or DOZEN bits
(CLKDIV<14:11>) may not execute properly. In
particular, for instructions that operate on an
SFR, data may not be read properly. Also, bits
automatically cleared in hardware may not be
cleared if the operation occurs during this
interval.
Work around
Always insert a NOP instruction before and after
either of the following:
•
•
Affected Silicon Revisions
BG
A2
A2
X
X
/2 or V
Enable
(CMCON<14> = 1) and map the output to a
pin with CN functionality or map an INTx
function to this same pin. This method only
consumes one I/O pin and requires no
external connections.
Monitor the pin for an interrupt event.
Enabling or disabling Doze mode by setting
or clearing the DOZEN bit
Before or after changing the DOZE<2:0> bits
CV
REF
BG
/6) are selected by the voltage refer-
+
the
input
comparator’s
works
as
REF
previously
- input,
output
BG
,
11. Module: Oscillator (Two-Speed Start-up)
12. Module: A/D Converter
Two-Speed Start-up is not functional. Leaving
the IESO Configuration bit in its default state
(Two-Speed Start-up enabled) may result in
unpredictable operation.
Work around
None. Always program the IESO Configuration
bit to disable the feature (CW2<15> = 0).
Affected Silicon Revisions
When using PGEC3 and PGED3 to debug an
application, all voltage references will be disabled.
This includes V
A/D conversion will always equal 03FFh.
Work around
Use either PGEC1/PGED1 or PGEC2/PGED2
to debug any A/D functionality.
Affected Silicon Revisions
A2
A2
X
X
PIC24FJ64GB004
REF
+, V
REF
-, AV
DD
DS80487F-page 5
and AV
SS
. Any