PIC16F73-I/SS Microchip Technology, PIC16F73-I/SS Datasheet - Page 304

• Manufacturer Part Number: PIC16F73-I/SS
• Description: IC MCU FLASH 4KX14 A/D 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F73-I/SS

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC16F
• No. Of I/o's: 22
• Ram Memory Size: 192Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164307 - MODULE SKT FOR PM3 28SSOPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PICmicro MID-RANGE MCU FAMILY
17.4.5
DS31017A-page 17-28
SDA
SCL
Master Mode
Master mode of operation is supported by interrupt generation on the detection of the START and
STOP conditions. The STOP (P) and START (S) bits are cleared from a reset or when the SSP
module is disabled. Control of the I
with both the S and P bits clear.
In master mode the SCL and SDA lines are manipulated by the SSP hardware.
The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge Transmit
• Repeated Start
Figure 17-17: SSP Block Diagram (I 2 C Master Mode)
SDA in
Bus Collision
SCL in
Read
MSb
Write collision detect
end of XMIT/RCV
Start bit, Stop bit,
State counter for
Clock Arbitration
Start bit detect
Stop bit detect
Acknowledge
Generate
SSPBUF
SSPSR
Preliminary
2
C bus may be taken when the P bit is set, or the bus is idle
LSb
Write
clock
data bus
shift
Internal
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
1997 Microchip Technology Inc.
SSPADD<6:0>
SSPM3:SSPM0
Baud
rate
generator