PIC16F84A-20/SS Microchip Technology, PIC16F84A-20/SS Datasheet - Page 659

IC MCU FLASH 1KX14 EE 20SSOP

PIC16F84A-20/SS

Manufacturer Part Number
PIC16F84A-20/SS
Description
IC MCU FLASH 1KX14 EE 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F84A-20/SS

Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
13
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
20-SSOP
Controller Family/series
PIC16F
No. Of I/o's
13
Eeprom Memory Size
64Byte
Ram Memory Size
68Byte
Cpu Speed
20MHz
No. Of Timers
1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPI3-DB16F84A - BOARD DAUGHTER ICEPIC3AC164307 - MODULE SKT FOR PM3 28SSOPAC164018 - MODULE SKT PROMATEII 20SSOP
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Transfer direction of data and acknowledgment bits depends on R/W bits.
Sr
Combined format - A master addresses a slave with a 10-bit address, then transmits
1997 Microchip Technology Inc.
Combined format:
S
(Code + A9:A8)
Slave Address
From slave to master
From master to slave
Slave Address R/W A Data A/A Sr
(write)
(read)
R/W A
data to this slave and reads data from this slave.
When a master does not wish to relinquish the bus (which occurs by generating a STOP condi-
tion), a repeated START condition (Sr) must be generated. This condition is identical to the start
condition (SDA goes high-to-low while SCL is high), but occurs after a data transfer acknowledge
pulse (not the bus-free state). This allows a master to send “commands” to the slave and then
receive the requested information or to address a different slave device. This sequence is shown
in
Figure A-8:
Figure
Slave Address
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
(A7:A0)
A-8.
Sr = repeated
Start Condition
(n bytes + acknowledge)
(read or write)
Combined Format
Slave Address R/W A Data A/A
A
Data
A
(write)
Data A/A
Direction of transfer
may change at this point
Sr Slave Address
(Code + A9:A8)
P
(read)
Appendix A
R/W A Data A
DS31034A-page 34-7
Data
A P
34

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