PIC18F4431-I/P Microchip Technology, PIC18F4431-I/P Datasheet - Page 259
![IC PIC MCU FLASH 8KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F4431-I/P
Manufacturer Part Number
PIC18F4431-I/P
Description
IC PIC MCU FLASH 8KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(40 pages)
8.PIC18F2431-ISP.pdf
(396 pages)
Specifications of PIC18F4431-I/P
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART/I2C/SPI/SSP
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
40PDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18LF2331-ISO PDF datasheet #7
- PIC18F2431-ISP PDF datasheet #8
- Current page: 259 of 396
- Download datasheet (8Mb)
20.9
Figure 20-3 shows the operation of the A/D converter
after the GO bit has been set and the ACQT2:ACQT0
bits are cleared. A conversion is started after the follow-
ing instruction to allow entry into Sleep mode before the
conversion begins. The internal A/D RC oscillator must
be selected to perform a conversion in Sleep.
Figure 20-4 shows the operation of the A/D converter
after the GO bit has been set and the ACQT3:ACQT0
bits are set to ‘010’, and selecting a 4 T
time before the conversion starts.
FIGURE 20-3:
FIGURE 20-4:
2003 Microchip Technology Inc.
GO bit is set,
and holding
cap is
disconnected
from analog
input
A/D triggered
Note 1:
1
A/D Conversions
Note 1:
T
Automatic
Acquisition
Time
ACQT
2
In continuous modes, next conversion starts at the end of T
Cycles
Conversion time is a minimum of 11 T
Conversion Starts
3
A/D CONVERSION T
A/D CONVERSION T
T
AD
b9
1 T
4
AD
b8
Conversion Starts
(Holding capacitor is disconnected)
2 T
T
AD
b9
1 T
AD
b7
AD
3 T
AD
b8
acquisition
2 T
AD
b6
PIC18F2331/2431/4331/4431
Go bit cleared on the rising edge of Q1 after the first Q3
following T
AD
AD
4 T
AD
b7
CYCLES (A
CYCLES (A
Preliminary
3 T
AD
b5
5 T
AD
b6
AD
Go bit cleared on the rising edge of Q1 after the first Q3
following T
4 T
AD
b4
AD
11
6 T
T
(1)
AD
+ 2 T
b5
AD
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The resulting buffer loca-
tion will contain the partially completed A/D conversion
sample. This will not set the ADIF flag, therefore, the
user must read the buffer location before a conversion
sequence overwrites it.
After the A/D conversion is completed or aborted, a
2 T
be started. After this wait, acquisition on the selected
channel is automatically started.
, and result buffer is loaded.
CQT
5 T
AD
CQT
b3
Cycles
Note:
AD
CY
7 T
AD
<2:0> = 000, T
AD
b4
, and a maximum of 11 T
<3:0> = 0010, T
11
wait is required before the next acquisition can
6 T
AD
b2
(1)
8
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
and result buffer is loaded.
AD
b3
T
7 T
AD
AD
b1
12.
9 T
AD
b2
AD
8
ACQ
b0
10
T
ACQ
AD
b1
T
AD
= 0)
9 T
11
AD
= 4 T
AD
b0
+ 6 T
10
DS39616B-page 257
AD
T
AD
CY
)
.
11
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