PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 474

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
Timer2 .............................................................................. 177
Timer3 .............................................................................. 179
Timer4 .............................................................................. 183
Timing Diagrams
DS39762E-page 474
TMR1H Register ...................................................... 171
TMR1L Register ....................................................... 171
Use as a Clock Source ............................................ 173
Use as a Real-Time Clock ....................................... 174
Associated Registers ............................................... 178
Interrupt .................................................................... 178
Operation ................................................................. 177
Output ...................................................................... 178
PR2 Register .................................................... 190, 197
TMR2 to PR2 Match Interrupt .................................. 197
16-Bit Read/Write Mode ........................................... 181
Associated Registers ............................................... 181
Operation ................................................................. 180
Oscillator .......................................................... 179, 181
Overflow Interrupt ............................................ 179, 181
Resetting Using the ECCPx Special Event Trigger . 181
TMR3H Register ...................................................... 179
TMR3L Register ....................................................... 179
Associated Registers ............................................... 184
MSSPx Clock, Output .............................................. 184
Operation ................................................................. 183
Postscaler. See Postscaler, Timer4.
PR4 Register .................................................... 183, 190
Prescaler. See Prescaler, Timer4.
TMR4 Register ......................................................... 183
TMR4 to PR4 Match Interrupt .......................... 183, 184
A/D Conversion ........................................................ 450
Asynchronous Reception, RXDTP = 0 (RXx Not Invert-
Asynchronous Transmission (Back-to-Back), TXCKP = 0
Asynchronous Transmission, TXCKP = 0
Automatic Baud Rate Calculation ............................ 314
Auto-Wake-up Bit (WUE) During Normal Operation 321
Auto-Wake-up Bit (WUE) During Sleep ................... 321
Baud Rate Generator with Clock Arbitration ............ 291
BRG Overflow Sequence ......................................... 314
BRG Reset Due to SDAx Arbitration During
Capture/Compare/PWM (Including ECCPx Modules) ....
CLKO and I/O .......................................................... 435
Clock Synchronization ............................................. 284
Clock/Instruction Cycle .............................................. 78
EUSARTx Synchronous Receive
EUSARTx Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 441
Example SPI Master Mode (CKE = 1) ..................... 442
Example SPI Slave Mode (CKE = 0) ....................... 443
Example SPI Slave Mode (CKE = 1) ....................... 444
External Clock (All Modes Except PLL) ................... 433
External Memory Bus for Sleep
External Memory Bus for TBLRD
Fail-Safe Clock Monitor ............................................ 361
ed) .................................................................... 319
(TXx Not Inverted) ............................................ 316
(TXx Not Inverted) ............................................ 316
Start Condition ................................................. 300
(Master/Slave) .................................................. 449
(Master/Slave) .................................................. 449
(Extended Microcontroller Mode) ............. 116, 118
(Extended Microcontroller Mode) ............. 116, 118
.......................................................................... 440
First Start Bit ............................................................ 292
Full-Bridge PWM Output .......................................... 201
Half-Bridge PWM Output ......................................... 200
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Master SSP I
Master SSP I
Parallel Slave Port (PSP) Read ............................... 165
Parallel Slave Port (PSP) Write ............................... 164
Program Memory Read ........................................... 436
Program Memory Write ............................................ 437
PWM Auto-Shutdown (P1RSEN = 0,
PWM Auto-Shutdown (P1RSEN = 1,
PWM Direction Change ........................................... 203
PWM Direction Change at Near 100% Duty Cycle .. 203
PWM Output ............................................................ 190
Repeated Start Condition ........................................ 293
Reset, Watchdog Timer (WDT), Oscillator Start-up Timer
Send Break Character Sequence ............................ 322
Slave Synchronization ............................................. 265
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 264
SPI Mode (Slave Mode, CKE = 0) ........................... 266
SPI Mode (Slave Mode, CKE = 1) ........................... 266
Synchronous Reception (Master Mode, SREN) ...... 325
Synchronous Transmission ..................................... 323
Synchronous Transmission (Through TXEN) .......... 324
Time-out Sequence on Power-up (MCLR Not Tied to
Time-out Sequence on Power-up (MCLR Not Tied to
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Acknowledge Sequence .................................... 297
C Bus Collision During a Repeated Start Condition
C Bus Collision During a Repeated Start Condition
C Bus Collision During a Stop Condition
C Bus Collision During a Stop Condition
C Bus Collision During Start Condition
C Bus Collision During Start Condition
C Bus Collision for Transmit and Acknowledge .... 298
C Bus Data ............................................................ 445
C Bus Start/Stop Bits ............................................ 445
C Master Mode (7 or 10-Bit Transmission) ........... 295
C Master Mode (7-Bit Reception) .......................... 296
C Slave Mode (10-Bit Reception, SEN = 0,
C Slave Mode (10-Bit Reception, SEN = 0) .......... 280
C Slave Mode (10-Bit Reception, SEN = 1) .......... 286
C Slave Mode (10-Bit Transmission) .................... 282
C Slave Mode (7-Bit Reception, SEN = 0, ADMSK =
C Slave Mode (7-Bit Reception, SEN = 0) ............ 277
C Slave Mode (7-Bit Reception, SEN = 1) ............ 285
C Slave Mode (7-Bit Transmission) ...................... 279
C Slave Mode General Call Address Sequence (7 or
C Stop Condition Receive or Transmit Mode ........ 297
(Case 1) ........................................................... 301
(Case 2) ........................................................... 301
(Case 1) ........................................................... 302
(Case 2) ........................................................... 302
(SCLx = 0) ....................................................... 300
(SDAx Only) ..................................................... 299
ADMSK = 01001) ............................................ 281
01011) ............................................................. 278
10-Bit Addressing Mode) ................................. 287
Auto-Restart Disabled) .................................... 206
Auto-Restart Enabled) ..................................... 206
(OST) and Power-up Timer (PWRT) ............... 438
V
V
V
DD
DD
DD
), Case 1 ..................................................... 60
), Case 2 ..................................................... 61
Rise > T
2
2
C Bus Data ........................................ 447
C Bus Start/Stop Bits ........................ 447
PWRT
© 2009 Microchip Technology Inc.
) ............................................ 61
DD
,