PIC16F84-10I/SO Microchip Technology, PIC16F84-10I/SO Datasheet - Page 35

• Manufacturer Part Number: PIC16F84-10I/SO
• Description: IC MCU FLASH 1KX14 EE 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F84-10I/SO

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 68 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC16F
• No. Of I/o's: 13
• Eeprom Memory Size: 64Byte
• Ram Memory Size: 68Byte
• Cpu Speed: 10MHz
• No. Of Timers: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MIL309-1075 - ADAPTER 18-SOIC TO 18-SOIC309-1011 - ADAPTER 18-SOIC TO 18-DIP309-1010 - ADAPTER 18-SOIC TO 18-DIPAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

7.5
Depending on the application, good programming prac-
tice may dictate that the value written to the Data
EEPROM should be verified (Example 7-1) to the
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
near the specification limit. The Total Endurance disk
will help determine your comfort level.
Generally the EEPROM write failure will be a bit which
was written as a ’1’, but reads back as a ’0’ (due to
leakage off the bit).
EXAMPLE 7-1:
READ
;
; Is the value written (in W reg) and
;
;
TABLE 7-1
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’, q = value depends upon condition. Shaded cells are not
1998 Microchip Technology Inc.
Address
08h
09h
88h
89h
BCF
:
:
MOVF
BSF
BSF
BCF
read (in EEDATA) the same?
Write Verify
used by Data EEPROM.
STATUS, RP0 ; Bank 0
EEDATA, W
STATUS, RP0 ; Bank 1
EECON1, RD
STATUS, RP0 ; Bank 0
Name
EECON1
EECON2
EEDATA
EEADR
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
WRITE VERIFY
EEPROM data register
EEPROM address register
EEPROM control register 2
Bit 7
—
; Any code can go here
;
; Must be in Bank 0
; YES, Read the
;
value written
Bit 6
—
Bit 5
—
Bit 4
EEIF
WRERR
Bit 3
7.6
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
7.7
When the device is code protected, the CPU is able to
read and write unscrambled data to the Data EEPROM.
For ROM devices, there are two code protection bits
(Section 8.1). One for the ROM program memory and
one for the Data EEPROM memory.
WREN
Bit 2
SUBWF EEDATA, W
BTFSS STATUS, Z
GOTO
:
:
Protection Against Spurious Writes
Data EEPROM Operation during Code
Protect
WRITE_ERR
Timer
Bit 1
WR
(72
Bit 0
RD
;
; Is difference 0?
; NO, Write error
; YES, Good write
; Continue program
ms
PIC16F8X
xxxx xxxx
xxxx xxxx
---0 x000
---- ----
Power-on
Value on
duration)
Reset
DS30430C-page 35
other resets
Value on all
uuuu uuuu
uuuu uuuu
---0 q000
---- ----
prevents