PIC24FJ256GB106-I/PT Microchip Technology, PIC24FJ256GB106-I/PT Datasheet - Page 112

• Manufacturer Part Number: PIC24FJ256GB106-I/PT
• Description: IC PIC MCU FLASH 256K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GB106-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 256KB (85.5K x 24)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240011 - KIT STARTER MPLAB FOR PIC24F MCUMA240014 - MODULE PLUG-IN PIC24
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ256GB110 FAMILY
7.1
The system clock source can be provided by one of
four sources:
• Primary Oscillator (POSC) on the OSCI and
• Secondary Oscillator (SOSC) on the SOSCI and
• Fast Internal RC (FRC) Oscillator
• Low-Power Internal RC (LPRC) Oscillator
The primary oscillator and FRC sources have the
option of using the internal USB PLL block, which
generates both the USB module clock and a separate
system clock from the 96 MHZ PLL. Refer to
Section 7.5 “Oscillator Modes and USB Operation”
for additional information.
The internal FRC provides an 8 MHz clock source. It
can optionally be reduced by the programmable clock
divider to provide a range of system clock frequencies.
The selected clock source generates the processor
and peripheral clock sources. The processor clock
source is divided by two to produce the internal instruc-
tion cycle clock, F
cycle clock is also denoted by F
instruction cycle clock, F
OSCO I/O pin for some operating modes of the primary
oscillator.
TABLE 7-1:
DS39897B-page 110
Fast RC Oscillator with Postscaler
(FRCDIV)
(Reserved)
Low-Power RC Oscillator (LPRC)
Secondary (Timer1) Oscillator
(SOSC)
Primary Oscillator (XT) with PLL
Module (XTPLL)
Primary Oscillator (EC) with PLL
Module (ECPLL)
Primary Oscillator (HS)
Primary Oscillator (XT)
Primary Oscillator (EC)
Fast RC Oscillator with PLL Module
(FRCPLL)
Fast RC Oscillator (FRC)
Note 1:
OSCO pins
SOSCO pins
2:
CPU Clocking Scheme
Oscillator Mode
OSCO pin function is determined by the OSCIOFCN Configuration bit.
This is the default oscillator mode for an unprogrammed (erased) device.
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
CY
. In this document, the instruction
OSC
/2, can be provided on the
OSC
/2. The internal
Oscillator Source
Secondary
Primary
Primary
Primary
Primary
Primary
Internal
Internal
Internal
Internal
Internal
Preliminary
7.2
The oscillator source (and operating mode) that is
used at a device Power-on Reset event is selected
using Configuration bit settings. The oscillator Config-
uration bit settings are located in the Configuration
registers
Section 25.1
details). The Primary Oscillator Configuration bits,
POSCMD1:POSCMD0 (Configuration Word 2<1:0>),
and the Initial Oscillator Select Configuration bits,
FNOSC2:FNOSC0
select the oscillator source that is used at a Power-on
Reset. The FRC primary oscillator with postscaler
(FRCDIV) is the default (unprogrammed) selection.
The secondary oscillator, or one of the internal
oscillators, may be chosen by programming these bit
locations.
The Configuration bits allow users to choose between
the various clock modes, shown in Table 7-1.
7.2.1
The
Word 2<7:6>) are used to jointly configure device clock
switching and the Fail-Safe Clock Monitor (FSCM).
Clock switching is enabled only when FCKSM1 is
programmed (‘0’). The FSCM is enabled only when
FCKSM1:FCKSM0 are both programmed (‘00’).
POSCMD1:
POSCMD0
FCKSM
11
xx
11
11
01
00
10
01
00
11
11
Initial Configuration on POR
in
CLOCK SWITCHING MODE
CONFIGURATION BITS
“Configuration
the
Configuration
program
(Configuration Word 2<10:8>),
© 2008 Microchip Technology Inc.
FNOSC2:
FNOSC0
111
110
101
100
011
011
010
010
010
001
000
memory
bits
Bits”
(Configuration
for
(refer
Note
1, 2
further
1
1
1
1
1
to