PIC18F4439-I/PT Microchip Technology, PIC18F4439-I/PT Datasheet - Page 21

• Manufacturer Part Number: PIC18F4439-I/PT
• Description: IC MCU FLASH 6KX16 EE A/D 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4439-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 640 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 640 B
• Interface Type: I2C, SPI, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• For Use With: 444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.2
Code memory is accessed one byte at a time, via the
4-bit command, ‘1001’ (Table Read, post-increment).
The contents of memory pointed to by the Table Pointer
(TBLPTRU:TBLPTRH:TBLPTRL) are loaded into the
Table Latch and then serially output on SDATA.
The 4-bit command is shifted in LSb first. The Table
Read is executed during the next 8 clocks, then shifted
out on SDATA during the last 8 clocks, LSb to MSb. A
TABLE 4-2:
FIGURE 4-3:
 2010 Microchip Technology Inc.
Step 1: Set Table Pointer.
Step 2: Read memory into Table Latch and then shift out on SDATA, LSb to MSb.
4-bit Command
SCLK
SDATA
0000
0000
0000
0000
0000
0000
1001
Read Code Memory, ID Locations,
and Configuration Bits
1
1
2
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
00 00
0
READ CODE MEMORY SEQUENCE
3
0
Data Payload
TABLE READ POST-INCREMENT INSTRUCTION TIMING (1001)
4
1
P5
SDATA = Input
1
2
3
MOVLW Addr[21:16]
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
TBLRD *+
4
5
6
Preliminary
7
8
P6
delay of P6 must be introduced after the falling edge of
the 8th SCLK of the operand to allow SDATA to
transition from an input to an output. During this time,
SCLK must be held low (see Table 4-2). This operation
also increments the Table Pointer by one, pointing to
the next byte in code memory for the next read.
This technique will work to read any memory in the
000000h to 3FFFFFh address space, so it also applies
to the reading of the ID and configuration registers.
9
LSb
P14
10 11
1
Core Instruction
2
SDATA = Output
12
Shift Data Out
3
13
4
14
5
PIC18FXX39
15 16
6
MSb
P5A
Fetch Next 4-bit Command
1
SDATA = Input
n
DS30480C-page 21
2
n
3
n
4
n