PIC18F4585-I/PT Microchip Technology, PIC18F4585-I/PT Datasheet - Page 4

• Manufacturer Part Number: PIC18F4585-I/PT
• Description: IC MCU FLASH 24KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4585-I/PT

• Core Size: 8-Bit
• Program Memory Size: 48KB (24K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3.25KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPI3-DB18F4680 - BOARD DAUGHTER ICEPIC3AC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2585/2680/4585/4680
16. Module: MSSP
TABLE 1:
17. Module: MSSP
DS80283E-page 4
Note 1:
In its current implementation, the I
mode operates as follows:
1. The Baud Rate Generator for I
RCEN becomes set when the system is idle. In
normal operation, the setting of RCEN should be
ignored by the module while the system is not idle.
Work around
Wait for the system to become idle. This requires
a check for the following bits to be reset:
ACKEN, RCEN, PEN, RSEN and SEN.
Date Codes that pertain to this issue:
All engineering and production devices.
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
mode is slower than the rates specified in
Table 17-3 of the Device Data Sheet.
For this revision of silicon, use the values
shown in Table 1 in place of those shown in
Table 17-3 of the Device Data Sheet. The
differences are shown in bold text.
4 MHz
4 MHz
4 MHz
F
OSC
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
I
2
2
C™ interface does not conform to the 400 kHz I
C™ CLOCK RATE w/BRG
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
F
CY
2
2
C in Master
C™ Master
20 MHz
20 MHz
20 MHz
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
F
CY
*2
18. Module: MSSP
2
C specification (which applies to rates greater than
2. Use the following formula in place of the one
In an I
unaddressed slave may respond to bus activity
when data on the bus matches its address. The
first occurrence will set the BF bit. The second
occurrence will set the BF and the SSPOV bits. In
both situations, the SSPIF bit is not set and an
interrupt will not occur. The device will vector to the
Interrupt Service Routine only if the interrupt is
enabled and an address match occurs.
Work around
The I
I
Date Codes that pertain to this issue:
All engineering and production devices.
2
C event to maintain normal operation.
SSPADD = INT((F
shown in Register 17-4 (SSPCON1) of the
Device
SSPM3:SSPM0 = 1000.
2
C slave must clear the SSPOV bit after each
2
C system with multiple slave nodes, an
BRG Value
0Eh
15h
59h
05h
08h
23h
01h
08h
00h
Data
© 2007 Microchip Technology Inc.
CY
Sheet
/F
SCL
(2 Rollovers of BRG)
) – (F
for
CY
400 kHz
400 kHz
333 kHz
312.5 kHz
bit
1 MHz
100 kHz
308 kHz
100 kHz
100 kHz
/1.111 MHz)) – 1
F
SCL
description,
(1)
(1)
(1)
(1)