PIC18F8722-I/PT Microchip Technology, PIC18F8722-I/PT Datasheet - Page 10
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PIC18F8722-I/PT
Manufacturer Part Number
PIC18F8722-I/PT
Description
IC PIC MCU FLASH 64KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.DV164136.pdf
(6 pages)
3.DV164136.pdf
(446 pages)
4.PIC18F8627T-IPT.pdf
(44 pages)
5.PIC18LF6627-IPT.pdf
(16 pages)
6.PIC18F8622-IPT.pdf
(448 pages)
Specifications of PIC18F8722-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
70
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183032, DM183022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164136 - DEVELOPMENT KIT FOR PIC18XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8722-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F8722-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC18F6627/6722/8627/8722
29. Module: MSSP (SPI Mode)
EXAMPLE 7:
30. Module: MSSP (SPI Mode)
TABLE 4:
DS80221C-page 10
Note 1:
In SPI mode, the Buffer Full Status bit, BF
(SSPxSTAT<0>), should not be polled in software
to determine when the transfer is complete.
Work around
Copy the SSPxSTAT register into a variable and
perform the bit test on the variable. In Example 7,
SSPxSTAT is copied into the working register
where the bit test is performed (SSP1STAT is
shown, but this process is also applicable to
SSP2STAT).
A second option is to poll the appropriate Master
Synchronous Serial Port Interrupt Flag bit,
SSPxIF. This bit can be polled and will set when
the transfer is complete.
Date Codes that pertain to this issue:
All engineering and production devices.
In SPI Master mode, a write collision may occur if
the SSPxBUF register is loaded immediately after
a transfer is complete. This may be caused by an
inadequate delay between the MSSP Interrupt
Flag bit (SSPxIF) or the Buffer Full bit (BF) being
set, and SSPxBUF being written to.
This has only been observed when the SPI clock
is
(SSPxCON1<3:0> = 001x).
loop_MSB:
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
4 MHz
4 MHz
4 MHz
operating
F
MOVF
BTFSS
BRA
OSC
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
I
2
2
C™ interface does not conform to the 400 kHz I
C™ CLOCK RATE w/BRG
SSP1STAT, W
WREG, BF
loop_MSB
at
F
OSC
10 MHz
10 MHz
10 MHz
/64
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
F
CY
or
((Timer2)/2)
20 MHz
20 MHz
20 MHz
F
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
CY
* 2
31. Module: MSSP (I
2
SSPxADD = INT((F
C specification (which applies to rates greater than
Work around
Add a software delay of one SCKx period after
detecting the completed transfer, and prior to
updating the contents of SSPxBUF.
Also verify that the Write Collision bit (WCOL) is
clear after writing SSPxBUF. If WCOL is set, clear
the bit in software and rewrite the contents of
SSPxBUF.
Date Codes that pertain to this issue:
All engineering and production devices.
In its current implementation, the I
operates as follows:
a)
b)
Date Codes that pertain to this issue:
All engineering and production devices.
The Baud Rate Generator for I
mode is slower than the rates specified in
Table 17-3 of the Device Data Sheet.
For this revision of silicon, use the values
shown in Table 4 (below) in place of those
shown in Table 17-3 of the Device Data Sheet.
The differences are shown in bold text.
Use the following formula in place of the
one shown in Register 19-4 (SSPxCON1)
of the Device Data Sheet for bit description
SSPM3:SSPM0 = 1000.
BRG Value
0Eh
15h
59h
05h
08h
23h
01h
08h
00h
CY
/F
© 2006 Microchip Technology Inc.
2
SCL
C™ Mode)
) – (F
(2 Rollovers of BRG)
CY
/1.111 MHz)) – 1
400 kHz
400 kHz
333 kHz
312.5 kHz
2
1 MHz
100 kHz
308 kHz
100 kHz
100 kHz
C Master mode
2
F
C in Master
SCL
(1)
(1)
(1)
(1)