LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 48

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 11.
T
[1]
[2]
[3]
Table 12.
T
[1]
LPC1769_68_67_66_65_64_4
Product data sheet
Symbol
f
t
t
Symbol
common to input and output
t
t
t
t
output
t
input
t
t
SCL
f
SU;DAT
r
f
WH
WL
v(Q)
su(D)
h(D)
amb
amb
Parameters are valid over operating temperature range unless otherwise specified.
CCLK = PCLK = 20 MHz; I
Bus capacitance C
CCLK = 20 MHz; peripheral clock to the I
signal in the I
=
=
−
−
40
40
°
°
Dynamic characteristic: I
Dynamic characteristics: I
Parameter
rise time
fall time
pulse width HIGH
pulse width LOW
data output valid time
data input set-up time
data input hold time
C to +85
C to +85
2
11.5 I
11.6 I
S-bus specification.
Parameter
SCL clock frequency
fall time
data set-up time
b
°
°
C; V
in pF (50 pF), external pull-up resistance = 218 Ω.
C.
2
2
Fig 12. I
DD(3V3)
C-bus
S-bus interface (LPC1769/68/67/66/65 only)
2
C-bus interface configured in master mode.
over specified ranges.
2
C-bus pins clock timing
2
C-bus pins (Fast-mode Plus)
2
Conditions
on pins I2STX_CLK and
I2SRX_CLK
on pins I2STX_CLK and
I2SRX_CLK
on pin I2STX_SDA;
on pin I2STX_WS
on pin I2SRX_SDA
on pin I2SRX_SDA
2
SDA
SCL
S-bus interface pins
S-bus interface PCLK =
P
Rev. 04 — 1 February 2010
[1][2][3]
Conditions
-
S
CCLK
⁄
4
; I
LPC1769/68/67/66/65/64
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
2
S clock cycle time T
Min
-
-
0.495 × T
-
-
-
3.5
4.0
Min
-
-
50
32-bit ARM Cortex-M3 microcontroller
cy(clk)
cy(clk)
Typ
-
-
-
-
-
-
-
-
= 1600 ns, corresponds to the SCK
Typ
-
-
-
t
f
t
Max
35
35
-
0.505 × T
30
30
-
-
SU;DAT
002aae860
© NXP B.V. 2010. All rights reserved.
Max
1
45
-
cy(clk)
Unit
ns
ns
-
ns
ns
ns
ns
ns
48 of 66
Unit
MHz
ns
ns