P80C552EBA/08,512 NXP Semiconductors, P80C552EBA/08,512 Datasheet - Page 16

• Manufacturer Part Number: P80C552EBA/08,512
• Description: IC 80C51 MCU 8BIT ROMLESS 68PLCC
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C552EBA/08,512

• Program Memory Type: ROMless
• Package / Case: 68-PLCC
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1235-5; 935262803512; P80C552EBA

Philips Semiconductors
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
A – Address
C – Clock
D – Input data
H – Logic level high
I – Instruction (program memory contents)
L – Logic level low, or ALE
P – PSEN
2002 Sep 03
PORT 0
PORT 2
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
PSEN
ALE
RD
PORT 0
PORT 2
PSEN
ALE
t
AVLL
FROM RI OR DPL
A0–A7
t
LLAX
t
t
AVWL
LHLL
t
t
LLWL
AVLL
t
LLAX
A0–A7
t
Figure 2. External Program Memory Read Cycle
t
P2.0–P2.7 OR A8–A15 FROM DPH
AVDV
RLAZ
t
Figure 3. External Data Memory Read Cycle
LLDV
t
LLPL
t
AVIV
t
LLIV
t
RLDV
A8–A15
t
PLAZ
t
RLRH
t
t
t
PLIV
PXIX
PLPH
INSTR IN
16
t
RHDX
DATA IN
Q – Output data
R – RD signal
t – Time
V – Valid
W – WR signal
X – No longer a valid logic level
Z – Float
Examples: t
t
PXIZ
t
RHDZ
t
t
WHLH
AVLL
LLPL
= Time for address valid to
= Time for ALE low to
PSEN low.
ALE low.
A0–A7
A0–A7 FROM PCL
A8–A15 FROM PCH
A8–A15
80C552/83C552
SU01694
SU01695
INSTR IN
Product data