STM32F105RBT6 STMicroelectronics, STM32F105RBT6 Datasheet - Page 59

• Manufacturer Part Number: STM32F105RBT6
• Description: MCU ARM 128KB FLASH MEM 64-LQFP
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F105RBT6

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, LIN, SPI, UART/USART, USB OTG
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 51
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: STM32F105x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, I2C, SPI, USART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 10
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit x 2, 16 Channel
• On-chip Dac: 12 bit x 2, 2 Channel
• For Use With: 497-10591 - DAUGHTER BOARD FOR STM32497-9040 - DEV KIT FOR STM32497-9041 - DEV KIT FOR STM32497-9042 - DEV KIT FOR STM32497-9043 - DEV KIT FOR STM32497-8924 - EVAL BOARD FOR STM32F107VCT497-8853 - BOARD DEMO STM32 UNIV USB-UUSCI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-8920

STM32F105xx, STM32F107xx
5.3.13
Figure 22. I/O AC characteristics definition
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
Unless otherwise specified, the parameters given in
performed under the ambient temperature and V
in
Table 38.
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
V
V
V
V
V
Table
NF(NRST)
IH(NRST)
IL(NRST)
Symbol
F(NRST)
hys(NRST)
to the series resistance must be minimum
R
PU
9.
(1)
(1)
(1)
(1)
PU
NRST pin characteristics
(see
NRST Input low level voltage
NRST Input high level voltage
NRST Schmitt trigger voltage
hysteresis
Weak pull-up equivalent resistor
NRST Input filtered pulse
NRST Input not filtered pulse
EXT ERNAL
OUTPUT
ON 50pF
Maximum frequency is achieved if (t r + t f ) 2/3)T and if the duty cycle is (45-55%)
Table
35).
Parameter
t r(I O)out
Doc ID 15274 Rev 5
(~10% order)
10%
50%
when loaded by 50pF
90%
(2)
.
V
Conditions
DD
V
DD
IN
T
10%
> 2.7 V
supply voltage conditions summarized

Table 38
V
50%
SS
90%
t r(I O)out
are derived from tests
–0.5
Min
300
30
2
Electrical characteristics
Typ
200
40
V
DD
Max
100
0.8
50
+0.5
ai14131
59/101
Unit
mV
k
ns
ns
V