MC9S08AC16CFJE Freescale Semiconductor, MC9S08AC16CFJE Datasheet - Page 57

IC MCU 8BIT 16K FLASH 32-LQFP

MC9S08AC16CFJE

Manufacturer Part Number
MC9S08AC16CFJE
Description
IC MCU 8BIT 16K FLASH 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets

Specifications of MC9S08AC16CFJE

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
S08AC
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
22
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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4.6
The FLASH module has nine 8-bit registers in the high-page register space, three locations in the
nonvolatile register space in FLASH memory which are copied into three corresponding high-page control
registers at reset. There is also an 8-byte comparison key in FLASH memory. Refer to
Table 4-4
control bits only by their names. A Freescale-provided equate or header file normally is used to translate
these names into the appropriate absolute addresses.
4.6.1
Bit 7 of this register is a read-only status flag. Bits 6 through 0 may be read at any time but can be written
only one time. Before any erase or programming operations are possible, write to this register to set the
frequency of the clock for the nonvolatile memory system within acceptable limits.
Table 4-7
Freescale Semiconductor
Reset
PRDIV8
DIV[5:0]
DIVLD
Field
5:0
7
6
W
R
FLASH Registers and Control Bits
for the absolute address assignments for all FLASH registers. This section refers to registers and
shows the appropriate values for PRDIV8 and DIV5:DIV0 for selected bus frequencies.
FLASH Clock Divider Register (FCDIV)
DIVLD
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for FLASH.
1 FCDIV has been written since reset; erase and program operations enabled for FLASH.
Prescale (Divide) FLASH Clock by 8
0 Clock input to the FLASH clock divider is the bus rate clock.
1 Clock input to the FLASH clock divider is the bus rate clock divided by 8.
Divisor for FLASH Clock Divider — The FLASH clock divider divides the bus rate clock (or the bus rate clock
divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV5:DIV0 field plus one. The resulting frequency of the
internal FLASH clock must fall within the range of 200 kHz to 150 kHz for proper FLASH operations.
Program/Erase timing pulses are one cycle of this internal FLASH clock which corresponds to a range of 5 μs to
6.7 μs. The automated programming logic uses an integer number of these pulses to complete an erase or
program operation. See
0
7
= Unimplemented or Reserved
PRDIV8
if PRDIV8 = 1 — f
if PRDIV8 = 0 — f
0
6
Figure 4-5. FLASH Clock Divider Register (FCDIV)
Table 4-6. FCDIV Register Field Descriptions
Equation
MC9S08AC16 Series Data Sheet, Rev. 8
DIV5
0
5
FCLK
4-1,
FCLK
Equation
= f
= f
Bus
DIV4
Bus
0
4
÷ (8 × ([DIV5:DIV0] + 1))
4-2, and
Description
÷ ([DIV5:DIV0] + 1)
Table
DIV3
3
0
4-6.
DIV2
0
2
DIV1
Table 4-3
0
1
Chapter 4 Memory
and
Eqn. 4-1
Eqn. 4-2
DIV0
0
0
57

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