C8051F236-GQ Silicon Laboratories Inc, C8051F236-GQ Datasheet - Page 40

• Manufacturer Part Number: C8051F236-GQ
• Description: IC 8051 MCU 8K FLASH 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F2xxr

Specifications of C8051F236-GQ

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 48-TQFP, 48-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 32
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F2x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F226DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 32 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1244

C8051F2xx
6.
Description
The ADC subsystem for the C8051F206 consists of configurable analog multiplexer (AMUX), a program-
mable gain amplifier (PGA), and a 100ksps, 12-bit successive-approximation-register ADC with integrated
track-and-hold and programmable window detector (see Figure 6.1). The AMUX, PGA, Data Conversion
Modes, and Window Detector are all configurable under software control via the Special Function Regis-
ter's shown in Figure 6.1. The ADC subsystem (ADC, track-and-hold and PGA) is enabled only when the
ADCEN bit in the ADC Control register (ADC0CN, Figure 6.5) is set to 1. The ADC subsystem is in low
power shutdown when this bit is 0.
6.1.
Any external port pin (ports 0-3) may be selected via software. The AMX0SL SFR is used to select the
desired analog input pin. (See SFR Definition 5.1). When the AMUX is enabled, the user selects which
port is to be used (bits PRTSL0–1), and then the pin in the selected port (bits PINSL0–2) to be the analog
input.
The PGA amplifies the AMUX output signal by an amount determined by the states of the AMPGN2–0 bits
in the ADC Configuration register, ADC0CF (SFR Definition 5.2). The PGA can be software-programmed
for gains of 0.5, 1, 2, 4, 8 or 16. It defaults to a gain of 1 on reset.
40
AIN31
AIN0
port pin may be configured
ADC (12-Bit, C8051F206 Only)
AIN0-31 are port 0-3
pins -- any external
as an analog input
Analog Multiplexer and PGA
Figure 6.1. 12-Bit ADC Functional Block Diagram
ADC0GTH
32-to-1
AMUX
AMX0SL
X
GND
ADC0GTL
+
-
GND
VDD
ADCEN
ADC0CF
Rev. 1.6
ADC0LTH
ADC
12-Bit
VDD
SAR
ADC0CN
VDD
ADC0LTL
12
VREF
24
12
T2 OV
Comp
Dig
ADWINT