DS80C411-FNY+ Maxim Integrated Products, DS80C411-FNY+ Datasheet

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... Selector Guide appears at end of data sheet ORDERING INFORMATION PART TEMP RANGE DS80C410-FNY -40°C to +85°C DS80C410-FNY+ -40°C to +85°C DS80C411-FNY -40°C to +85°C DS80C411-FNY+ -40°C to +85°C +Denotes a lead(Pb)-free/RoHS-compliant device 102 . PIN-PACKAGE 100 LQFP 100 LQFP 100 LQFP 100 LQFP ...

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ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Input Pin Relative to Ground………………………………………………………..-0.5V to +5.5V Voltage Range on Any Output Pin Relative to Ground……………………………………………..-0. Voltage Range on V Relative to Ground…………………………………………………………………..-0.5V to +3.6V CC3 Voltage Range on V Relative ...

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Specifications to -40°C are guaranteed by design and not production tested. Note 1: The user should note that this part is tested and guaranteed to operate down to V Note 2: thresholds for those supplies, V given supply is greater ...

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AC ELECTRICAL CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS 3.0V to 3.6V 1.8V ±10%, T CC3 CC1 PARAMETER External Crystal Frequency Clock Mutliplier 2X Mode Clock Multiplier 4X Mode External Clock Oscillator Frequency Clock Mutliplier 2X Mode Clock Multiplier ...

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EXTERNAL CLOCK OSCILLATOR (XTAL1) CHARACTERISTICS PARAMETER Clock Oscillator Period Clock Symmetry at 0 CC3 Clock Rise Time Clock Fall Time EXTERNAL CLOCK DRIVE t CF XTAL1 t CH SYSTEM CLOCK TIME PERIODS (t SYSTEM CLOCK SELECTION 4X/2X CD1 ...

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PARAMETER SYMBOL Data Float After RD (P3 RHDZ PSEN) High ALE Low to Valid Data In t LLDV Port 0 Address to Valid Data t AVDV0 In Port Address, Port 4 CE, or Port 5 ...

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7 of 102 ...

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8 of 102 ...

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MULTIPLEXED, 2-CYCLE DATA MEMORY PCE0-3 READ PORT 4 – CE0  3 PORT 6 – CE4  7 PORT 4/6 ADDRESS A16 -A21 MULTIPLEXED, 2-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0  3 PORT 6 – CE4  ...

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MULTIPLEXED, 2-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0  3 PORT 6 – CE4  7 PORT 4/6 ADDRESS A16 -A21 MULTIPLEXED, 3-CYCLE DATA MEMORY PCE0-3 READ OR WRITE PORT 4 – CE0  3 PORT 6 – ...

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MULTIPLEXED, 3-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0  3 PORT 6 – CE4  7 PORT 4/6 ADDRESS A16 -A21 MULTIPLEXED, 3-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0  3 PORT 6 – CE4  ...

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... A16 -A21 MULTIPLEXED, 9-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0  3 PORT 6 – CE4  7 PORT 4/6 A16 -A21 A16 -A21 ADDRESS DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN A16 -A21 A16 -A21 A16 -A21 12 of 102 A16 -A21 A16 -A21 ...

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MULTIPLEXED, 9-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0  3 PORT 6 – CE4  7 PORT 4/6 A16 -A21 A16 -A21 ADDRESS A16 -A21 13 of 102 A16 -A21 ...

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ELECTRICAL CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS 3.0V to 3.6V 1.8V ±10%, T CC3 CC1 PARAMETER External Crystal Frequency Clock Mutliplier 2X Mode Clock Multiplier 4X Mode External Oscillator Frequency Clock Mutliplier 2X Mode Clock Multiplier 4X Mode ...

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MOVX CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS 3.0V to 3.6V 1.8V +±10%, T CC3 CC1 PARAMETER Input Instruction Float After PSEN PSEN High to Data Address, Port 4 CE, Port 5 PCE Valid RD Pulse Width (P3.7 or ...

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AC electrical characteristics assume 50% duty cycle for the oscillator, oscillator frequency ≤ 75MHz, and are not 100% production Note 1: tested, but are guaranteed by design. All parameters apply to both commercial and industrial temperature operation, unless otherwise noted. ...

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17 of 102 ...

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18 of 102 l ...

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NONMULTIPLEXED, 2-CYCLE DATA MEMORY PCE0-3 READ OR WRITE PORT 4 – CE0  3 PORT 6 – CE4  7 PORT 4/6 ADDRESS A16 -A21 NONMULTIPLEXED, 2-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0  3 PORT 6 – ...

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NONMULTIPLEXED, 2-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0  3 PORT 6 – CE4  7 PORT 4/6 ADDRESS A16 -A21 PORT 7 NONMULTIPLEXED, 3-CYCLE DATA MEMORY PCE0-3 READ OR WRITE PORT 4 – CE0  3 PORT ...

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NONMULTIPLEXED, 3-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0  3 PORT 6 – CE4  7 PORT 4/6 ADDRESS A16 -A21 PORT 7 NONMULTIPLEXED, 3-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0  3 PORT 6 – ...

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... NONMULTIPLEXED, 9-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0  3 PORT 6 – CE4  7 PORT 4/6 ADDRESS A16 -A21 A16 -A21 PORT 7 DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN A16 -A21 A16 -A21 A16 -A21 22 of 102 A16 -A21 A16 -A21 ...

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NONMULTIPLEXED, 9-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0  3 PORT 6 – CE4  7 PORT 4/6 ADDRESS A16 -A21 PORT 7 OW PIN TIMING CHARACTERISTICS (Note 3.0V to 3.6V 1.8V ±10%, ...

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OW PIN TIMING 24 of 102 ...

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PIN TIMING CHARACTERISTICS OWSTP (V = 3.0V to 3.6V 1.8V ±10%, T CC3 CC1 PARAMETER Active Time for Presence Detect Active Time for Presence Detect Recovery Active Time for Write 1 Recovery (Notes 2, 3) Active Time for ...

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ETHERNET MII INTERFACE TIMING CHARACTERISTICS (V = 3.0V to 3.6V 1.8V ±10%, T CC3 CC1 PARAMETER TXClk Duty Cycle TXD, TX_EN Data Setup to TXClk TXD, TX_EN Data Hold from TXClk RXClk Pulse Width RXClk to RXD, RX_DV, ...

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SERIAL PORT MODE 0 TIMING CHARACTERISTICS (V = 3.0V to 3.6V 1.8V ±10%, T CC3 CC1 PARAMETER Serial Port Clock Cycle Time Output Data Setup to Clock Rising Output Data Hold from Clock Rising Input Data Hold After ...

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SERIAL PORT 0 (SYNCHRONOUS MODE) HIGH-SPEED OPERATION, TXD CLK = SYSCLK/4 (SM2 = 1) TRADITIONAL 8051 OPERATION, TXD CLOCK = XTAL/12 (SM2 = 102 ...

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POWER-CYCLE TIMING CHARACTERISTICS PARAMETER Crystal Startup Time (Note 1) Power-On Reset Delay (Note 2) Note 1: Startup time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592MHz crystal manufactured by Fox Electronics. Note 2: Reset ...

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... BLOCK DIAGRAM 1-WIRE CONTROLLER PORT LATCH PORT 5 P5.0–P5.7 DS80C410 DS80C411 DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN P1.0–P1.7 PORT 1 SERIAL PORT 1 PORT LATCH TIMER 102 P0.0–P0.7 PORT 0 ...

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PIN DESCRIPTION PIN NAME 70 V +1.8V Core Supply Voltage CC1 12, 36, 62, V +3.3V I/O Supply Voltage CC3 87 13, 39, 63, V Digital Circuit Ground SS 88 Address Latch Enable, Output. When the MUX pin is low, ...

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... P5.3 Port Alternate Function P5.0 C0TX CAN0 Transmit Output – Unavailable on DS80C411 31 P5.4 P5.1 C0RX CAN0 Receive Input – Unavailable on DS80C411 P5.2 T3 Timer 3 External Input 30 P5.5 P5.3 None PCE0 Peripheral Chip Enable 0 P5.4 29 P5.6 PCE1 Peripheral Chip Enable 1 P5 ...

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PIN NAME CE7 Program Memory Chip Enable 7 P6.3 50 P6.6 P6.4 A20 Program/Data Memory Address 20 P6.5 A21 Program/Data Memory Address 21 P6.6 RXD2 Serial Port 2 Receive 49 P6.7 P6.7 TXD2 Serial Port 2 Transmit Port 7, I/O. ...

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PIN NAME MII Management Input/Output. The MII management I/O is the data pin for serial communication with the external Ethernet PHY controller read cycle, data is driven by the PHY to the MAC synchronously with 19 MDIO respect ...

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... TERMINOLOGY The term DS80C410 is used in the remainder of the document to refer to the DS80C410 and DS80C411 unless otherwise specified. DETAILED DESCRIPTION The DS80C410 network microcontroller offers the highest integration available in an 8051 device. Peripherals include a 10/100 Ethernet MAC, three serial ports, an optional CAN 2.0B controller, 1-Wire Master, and 64 I/O pins. ...

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For example, 40MHz standard operation has a machine cycle rate of 10MHz. In PMM, at the same external clock speed, software can select a 39kHz machine cycle rate, considerably reducing power ...

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... SFRs contained in the standard 80C32. High-Speed Microcontroller User’s Guide: Network Microcontroller Supplement contains a full description of all SFRs. Bits that are related to the CAN module become read-only bits on the DS80C411, returning logic 1 when read. Exceptions to this are:  C0_I/O (P5CNT. general-purpose read/write bit on the DS80C411, but it has no effect on processor operation.  ...

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Table 1. SFR Addresses and Bit Locations REGISTER BIT 7 BIT 6 P4 P4.7/A19 P4.6/A18 SP DPL DPH DPL1 DPH1 DPS ID1 ID0 PCON SMOD_0 SMOD0 TCON TF1 TR1 C/ T TMOD GATE TL0 TL1 TH0 TH1 CKCON WD1 WD0 ...

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REGISTER BIT 7 BIT 6 C0M9C MSRDY ETI C0M10C MSRDY ETI IP — PS1 SADEN0 SADEN1 C0M11C MSRDY ETI C0M12C MSRDY ETI C0M13C MSRDY ETI C0M14C MSRDY ETI C0M15C MSRDY ETI SCON1 SM0/FE_1 SM1_1 SBUF1 PMR CD1 CD0 STATUS PIP ...

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REGISTER BIT 7 BIT 6 DPL3 DPH3 DPS1 ID3 ID2 STATUS1 — — EIP EPMIP C0IP P7 P7.7/A7 P7.6/A6 TL3 TH3 T3CM TF3 TR3 SCON2 SM0/FE_2 SM1_2 SBUF2 Note: Shaded bits are timed-access protected. BIT 5 BIT 4 BIT 3 ...

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Table 2. SFR Reset Values REGISTER BIT 7 BIT DPL 0 0 DPH 0 0 DPL1 0 0 DPH1 0 0 DPS 0 0 PCON 0 0 TCON 0 0 TMOD 0 0 ...

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REGISTER BIT 7 BIT 6 STATUS 0 0 MCON T2CON 0 0 T2MOD 1 1 RCAP2L 0 0 RCAP2H 0 0 TL2 0 0 TH2 0 0 COR 0 1 PSW 0 0 MCNT0 0 ...

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... SRAM configurable as extended stack memory or MOVX data memory  256 Bytes of RAM reserved for the CAN message centers (not available on the DS80C411)  64kB embedded ROM firmware Up to 16MB of external code memory can be addressed through a multiplexed or demultiplexed 22-bit address bus/8-bit data bus through eight available chip enables ...

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ADDRESSING MODES Three different addressing modes are supported, as selected by the AM1, AM0 bits in the address control (ACON; 9Dh) SFR. AM1:0 00b 16-bit (default when internal ROM disabled) 01b 1xb 24-bit contiguous (default if internal ROM enabled) 16-Bit ...

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Table 3. Extended Address Generation P4CNT.5–3 P6.5 000 I/O 001 I/O 010 I/O 011 I/O 100 I/O 101 I/O 110 or 111(default) A21 Table 4. Chip-Enable Generation PORT 6 PIN FUNCTION P6CNT.2–0 P6.3 P6.2 000 (Note 3) I/O I/O 100 ...

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Table 6. External Memory Addressing Pin Assignments SIGNAL ADDRESS A15–A8 A7–A0 D7–D0 DATA CHIP ENABLES PCE3 PCE2 PERIPHERAL CHIP PCE1 ENABLES PCE0 Combined Program/Data Memory Access The DS80C410 can be configured to allow data memory access (MOVX) to the program ...

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... SFR address locations not used in the original 8051. To access the extended 24-bit address range supported by the DS80C410, a third, high-order byte (DPXn) has been added to each pointer so that each data pointer is now composed of the SFR combination DPXn+DPHn+DPLn. up each data pointer. DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN PROGRAM MEMORY = ...

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Table 8. Data Pointer SFR Locations DATA POINTER DPX+DPH+DPL COMBINATION DPTR0 DPX (93h) + DPH (83h) + DPL (82h) DPTR1 DPX1 (95h) + DPH1 (85h) + DPL1 (84h) DPTR2 DPX2 (EBh) + DPH2 (F3h) + DPL2 (F2h) DPTR3 DPX3 (EDh) ...

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Auto-Increment/Decrement (if AID = 1) MOVC A, @A+DPTR MOVX A, @DPTR MOVX @DPTR, A When used in conjunction, the auto-toggle and auto-increment/decrement features can produce very fast and efficient routines for copying or moving data. For example, suppose you want ...

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Table 9. Data Memory Cycle Stretch Values STRETCH MD2 MD1 MD0 VALUE (Note (Note ...

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The additional 256 Bytes of internal SRAM are used to configure and operate the 15 CAN- controller message centers. Extended Stack Pointer The DS80C410 supports both the traditional 8-bit and an extended 10-bit stack pointer that improves ...

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Table 11. Arithmetic Accelerator Sequencing DIVIDE (32/16 or 16/16) Load MA with dividend LSB Load MA with dividend LSB + Load MA with dividend LSB + 2 Load MA with dividend MSB. Load MB with ...

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... RECEIVE, AND FLOW CONTROL) NOTE: WHEN CONNECTING THE DS80C400 TO AN EXTERNAL PHY, DO NOT CONNECT THE RSTOL TO THE RESET OF THE PHY. DOING SO MAY DISABLE THE ETHERNET TRANSMIT. DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN POWER MANAGEMENT BLOCK CSR REGISTERS ADDRESS CHECK ...

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Buffer Control Unit The buffer control unit (BCU) serves as the central controller of all DS80C410 Ethernet activity. The BCU regulates CPU read/write activity to the Ethernet controller blocks through a series of SFRs: BCU control (BCUC; E7h), BCU data ...

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The BCU incorporates first-in-first-out receive packet register (receive FIFO) so that the CPU can access information for the next receive packet in queue. Upon reception of each valid packet into receive buffer memory, the BCU ...

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Each CSR register is documented as follows: MAC Control CSR Register: 00h Register Address: Bit Names BLE 23 DRO OM[1: — 7 BLOMT[1:0] Reset State ...

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IF, Inverse Filtering 0 = inverse filtering disabled (default inverse filtering by the address check block enabled PB, Pass Bad Frames 0 = packet filter bit in the receive status word is set (= 1) only when error-free ...

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MAC Address High CSR Register: 04h Register Address: Bit Names: 31 — — 23 — — Reset State PADR [47:32]m MAC Physical Address [47:32]. These two ...

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Multicast Address High CSR Register: 0Ch Register Address: Bit Names: 31 HT[63] HT[62] 23 HT[55] HT[54] 15 HT[47] HT[46] 7 HT[39] HT[38] Reset State [63:32], Hash Table ...

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MII Address CSR Register: 14h Register Address: Bit Names: 31 — — 23 — — 15 PHYA [4:0] 7 PHYR [1:0] Reset State PHYA[4:0], PHY Address [4:0]. This ...

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... Upon successful transmission of a pause-control frame, the BUSY bit returns to logic pause-control frame currently being transmitted (default initiate a pause-control frame Figure 4. Pause-Control Frame SFD PREAMBLE (7) (1) (6) DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN PAUSE [15:8] PAUSE [7:0] — — — — — — 0 ...

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VLAN1 Tag CSR Register: 20h Register Address: Bit Names: 31 — — 23 — — Reset State VLAN1 [15:0], VLAN1 Tag Identifier [15:0]. These 16 bits ...

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Wake-Up Frame Filter CSR Register: 28h Register Address: Bit Names Reset State WUFD [31:0], Wake-Up Frame Filter Data [31:0]. These 32 bits are used ...

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... WRITE * During a read operation, the external PHY drives the MDIO line low for the second bit of the turnaround field to indicate proper synchronization, and then drives the 16-bits of read data requested. DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN TXCLK TX_EN TXD[3:0] MII I/O BLOCK ...

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... VLAN tag protocol ID (= 8100h) is encountered where the Length or Type is normally expected. The frame is then considered to be VLAN tagged. The VLAN frame format is described later. Figure 7. IEEE 802.3 Ethernet Frame PREAMBLE SFD DESTINATION ADDRESS (7) (1) (6) DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN ETHERNET FRAME SOURCE ADDRESS TYPE/LENGTH (6) ( 102 Figure 7. ...

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... DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN shows the five bits controlling the destination address filter. HP (MAC Control.13) Hash/Perfect Filtering Mode HO (MAC Control.15) Hash-Only Filtering Mode IF (MAC Control.17) Inverse Filtering PR (MAC Control.18) Promiscuous Mode PM (MAC Control.19) Pass All Multicast DESTINATION ADDRESS FILTER CRITERIA ...

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Multicast Hash Filter Hash filtering of destination addresses requires that a hash table be established. The hash table must be programmed into the CSR multicast address low and multicast address high registers. When hash filtering has been selected, the 6 ...

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... Figure 11. Transmit/Receive Data Buffer Memory 8kB INTERNAL SRAM RECEIVE BUFFER (n PAGES) PAGE ( BUFFER SIZE PAGE ( SETTING (EBS.4–EBS.0) TRANSMIT BUFFER ( PAGES) DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN PAGE 0 PAGE PAGE PAGE 31 ...

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Transmit/Receive Status Words For each attempt made by the MAC to receive or transmit packet data, the BCU writes a 32-bit transmit or receive status word back to the first word of the starting page for the packet. This word ...

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NOCRS, No Carrier. This bit is only valid in half-duplex mode transmit frame was not aborted due to lack of carrier 1 = transmit frame aborted due to lack of carrier (CRS = 0 when transmit frame initiated) ...

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VLAN2, Two_Level VLAN Frame 0 = receive frame did not contain a VLAN tag that matched the VLAN2 register 1 = receive frame 13th and 14th bytes matched the two-level VLAN tag register (VLAN2) VLAN1, One_Level VLAN Frame 0 = ...

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Ethernet Interrupts The DS80C410 Ethernet controller supports two interrupt sources: Ethernet power-mode interrupt and the Ethernet activity interrupt. Each interrupt source has its own enable, priority, and flag bits. The locations of these bits are documented in the interrupt vector ...

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... NetBoot allows an application to be downloaded from the network and executed by the microcontroller. To use the ROM firmware, the system is required to have the following hardware components:  64kB SRAM memory, internal on the DS80C410 and DS80C411, mapped (Note 1) at address locations 000000h–00FFFFh  ...

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Figure 13. ROM Code Boot Sequence Figure 13 illustrates the ROM decisions 74 of 102 ...

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... Enables CE4–7, 1M/peripheral chip enable Merged program/data CE0–3, relocate internal XRAM Enables extended 1kB stack option Configure to maximum MOVX stretch value Configure UARTs for Mode 1 serial operation Figure 14. Memory Map Following Execution of ROM_Init on DS80C410/DS80C411 INTERNAL MEMORY program CAN/BCU XRAM ROM ...

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Serial Loader The serial loader function implemented by the firmware can be invoked by leaving the serial loader pin (P1.7) at logic 1 during the boot sequence. When this condition is found, the ROM monitors the RXD0 pin for reception ...

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NetBoot The NetBoot process affords the user flexibility to download or update code remotely over the network. This capability is quite powerful. Not only does it make firmware revisions trivial, but it also makes remote diagnostics very practical. Also, since ...

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... TFTP server the file ‘TINI400.’ Using this strategy, the TFTP server operator can distinguish between different devices and/or different releases of the Maxim Networked Microcontroller ROM firmware (DS80C400, DS80C410, and DS80C411). After successfully locating the desired file on the TFTP server, the DS80C410 must transfer and program the file into memory ...

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Figure 17. Maxim tbin2 Record and File Format tbin2 file tbin2 record tbin2 record tbin2 record tbin2 record . . . tbin2 record Find-User Code The DS80C410 ROM firmware attempts to find valid user code by searching for specific signature ...

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ROM function. Table 16 provided by the TCP/IP stack, socket layer, and task manager are included after the table, while the full details for these and other exported ROM functions are covered in the High-Speed Microcontroller User’s Guide: Network ...

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Table 16. ROM Export Table INDEX FUNCTION 0 Num_Fn,0,0 1 crc16 2 mem_clear 3 mem_copy 4 mem_compare 5 add_dptr0 6 add_dptr1 7 sub_dptr0 8 sub_dptr1 9 getpseudorandom 10 rom_kernelmalloc 11 rom_kernelfree 12 rom_malloc 13 rom_malloc_dirty 14 rom_free 15 rom_deref 16 ...

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INDEX FUNCTION 61 task_kill 62 task_suspend 63 task_sleep 64 task_signal 65 rom_task_switch_in 66 rom_task_switch_out 67 EnterCritSection 68 LeaveCritSection 69 rom_init 70 rom_copyivt 71 rom_redirect_init 72 mm_init 73 km_init 74 ow_init 75 network_init 76 eth_init 77 init_sockets 78 tick_init 79 WOS_Tick ...

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INDEX FUNCTION 122 Math_LongDiv1024 123 task_suspend_nc 123 task_sleep_nc 124 UDP_TestReceive 125 ETH_ReadMII 126 ETH_WriteMII 127 ETH_ReadCSR 128 ETH_WriteCSR 129 IP_CheckHeader 130 IP_PacketReceived DESCRIPTION/GROUP Task scheduler functions Socket function Ethernet MAC functions IP stack functions 83 of 102 ...

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TCP/IP Stack and Berkeley Sockets The ROM firmware implements TCP/IP Ethernet networking over an industry-standard/Berkeley socket interface. The stack supports TCP and UDP transport protocols, allowing a maximum of 24 client/server sockets for either IPv4 or IPv6. Table 17 lists ...

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... Controller Area Network (CAN) Module The DS80C410 incorporates one CAN controller that is fully compliant with the CAN 2.0B specification. On the DS80C411, the CAN controller is not available. CAN is a highly robust, high-performance communication protocol for serial communications. Popular in a wide range of applications including automotive, medical, heating, ventilation, and industrial control, the CAN architecture allows for the construction of sophisticated networks with a minimum of external hardware ...

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Modification of the CAN registers located in MOVX memory is protected through the SWINT bit. Consult the description of this bit in the High-Speed Microcontroller User’s Guide: Network Microcontroller Supplement for more information. The CAN module contains a block of ...

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CAN Interrupts The DS80C410 provides one interrupt source for the CAN controller. The CAN interrupt source can be triggered by a receive/transmit acknowledgment from one of the 15 message centers or an error condition. Each message center has individual ETI ...

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Table 19. Arbitration/Masking Feature Summary ARBITRATION TEST NAME REGISTERS Message Center Standard 11-bit Arbitration Registers 0–1 Arbitration (Located in each message (CAN 2.0A) center, MOVX memory) Message Center Extended 29-bit Arbitration Registers 0–3 Arbitration (Located in each message (CAN 2.0B) ...

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Error Counter Interrupt Generation The CAN module can be configured to alert the microcontroller when either 96 or 128 errors have been detected by the transmit or receive error counters. The error-count select bit, ERCS (C0C.1), selects whether the limit ...

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Clock Control All 1-Wire timing patterns are generated using a base clock of 1.0MHz. To create this base clock frequency for the 1-Wire bus master, the microcontroller system clock must be internally divided down. The clock divisor internal register implements ...

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RBF flag. Thus, if both RSRF and RBF are set, no further transmissions should be made on the 1-Wire bus, ...

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EN_FOW (Bit 2): Enable Force OW. Setting the EN_FOW bit to a logic 1 allows the bus master to force the OW line low using FOW (bit 2 of the command register). Clearing the EN_FOW bit to a logic 0 ...

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Table 22. 1-Wire Bus Master Interrupt Sources INTERRUPT SOURCE After a 1-Wire reset has been issued, this flag is set after the amount Presence Detect of time for a presence-detect pulse to have occurred. This bit is cleared when the ...

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Timers The microcontroller provides four general-purpose timer/counters. Timers 0, 1, and 3 have three common modes of operation. Each of the three can be used as a 13-bit timer/counter, 16-bit timer/counter, or 8-bit timer/counter with auto-reload. Timer 0 can also ...

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Table 25 demonstrates that, for a 40MHz crystal frequency, the watchdog timer is capable of producing timeout 17 periods from 3.28ms (2 x 1/40MHz) to greater than one and a half seconds (1. default setting of CD1:0 (= ...

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Table 26. Interrupt Summary NAME FUNCTION PFI Power-Fail Interrupt INT0 External Interrupt 0 TF0 Timer 0 INT1 External Interrupt 1 TF1 Timer 1 TI0 or RI0 Serial Port 0 TF2 Timer 2 TI1 or RI1 Serial Port 1 INT2 External ...

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Repeat steps 2, 3 over the message data for which the checksum computed  Read MSB of 16-bit value from OCAD  One’s complement of the byte last read is the Internet checksum MSB  Read ...

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Changing the System Clock/Machine Cycle Clock Frequency The microcontroller incorporates a special locking sequence to ensure “glitch-free” switching of the internal clock signals. All changes to the CD1, CD0 bits must pass through the 10 (divide-by-4) state. For example, to ...

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Status The STATUS (C5h) register and STATUS1 (F7h) register provide information about interrupt and serial port activity to assist in determining possible to enter PMM. The microcontroller supports three levels of interrupt priority: power-fail, high, and low. ...

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External Reset Pins The DS80C410 has both reset input (RST) and reset output ( RSTOL ) pins. The RSTOL pin supplies an active-low reset output when the microcontroller is reset through a high on the RST pin, a timeout of ...

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... DS80C411 25 26 LQFP REVISION HISTORY SELECTOR GUIDE PART 76 DS80C410-FNY 75 DS80C410+FNY DS80C411-FNY DS80C411+FNY + Denotes a lead(Pb)-free/RoHS-compliant device. PACKAGE INFORMATION For the latest package outline information and land patterns www.maxim-ic.com/packages PACKAGE TYPE 100 LQFP 51 50 TINI is a registered trademark of Maxim Integrated Products, Inc. ...

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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time © 2009 Maxim Integrated Products DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN DESCRIPTION 102 of 102 Maxim is a registered trademark of Maxim Integrated Products, Inc. ...