PIC18F67J50-I/PT Microchip Technology, PIC18F67J50-I/PT Datasheet - Page 35

• Manufacturer Part Number: PIC18F67J50-I/PT
• Description: IC PIC MCU FLASH 64KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F67J50-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 49
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C/MSSP/SPI/EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.0
2.1
Devices in the PIC18F87J10 family incorporate a
different oscillator and microcontroller clock system
than general purpose PIC18F devices. The addition of
the USB module, with its unique requirements for a
stable clock source, make it necessary to provide a
separate clock source that is compliant with both USB
low-speed and full-speed specifications.
The PIC18F87J50 family has additional prescalers and
postscalers which have been added to accommodate a
wide range of oscillator frequencies. An overview of the
oscillator structure is shown in Figure 2-1.
Other oscillator features used in PIC18 enhanced
microcontrollers, such as the internal oscillator block
and clock switching, remain the same. They are
discussed later in this chapter.
2.1.1
The operation of the oscillator in PIC18F87J10 family
devices is controlled through three Configuration regis-
ters and two control registers. Configuration registers,
CONFIG1L, CONFIG1H and CONFIG2L, select the
oscillator mode, PLL prescaler and CPU divider options.
As Configuration bits, these are set when the device is
programmed and left in that configuration until the
device is reprogrammed.
The OSCCON register (Register 2-2) selects the Active
Clock mode; it is primarily used in controlling clock
switching in power-managed modes. Its use is
discussed in Section 2.4.1 “Oscillator Control
Register”.
The OSCTUNE register (Register 2-1) is used to trim
the INTOSC frequency source, as well as select the
low-frequency clock source that drives several special
features. The OSCTUNE register is also used to
activate or disable the PLL. Its use is described in
Section 2.2.5.1 “OSCTUNE Register”.
2.2
PIC18F87J10 family devices can be operated in eight
distinct oscillator modes. Users can program the
FOSC2:FOSC0 Configuration bits to select one of the
modes listed in Table 2-1. For oscillator modes which
produce a clock output, “CLKO”, on pin RA6, the output
frequency will be one fourth of the peripheral clock
frequency. The clock output will stop when in Sleep
mode, but will continue during Idle mode (see
Figure 2-1).
© 2009 Microchip Technology Inc.
OSCILLATOR
CONFIGURATIONS
Overview
Oscillator Types
OSCILLATOR CONTROL
PIC18F87J50 FAMILY
TABLE 2-1:
INTOSCPLLO Internal Oscillator mode, PLL can be
INTOSCPLL Internal Oscillator mode, PLL can be
INTOSCO
INTOSC
ECPLL
HSPLL
Mode
EC
HS
External Clock Input mode, the PLL can
be enabled or disabled, CLKO on RA6,
apply external clock signal to RA7
External Clock Input mode, the PLL is
always disabled, CLKO on RA6, apply
external clock signal to RA7
High-Speed Crystal/Resonator mode,
PLL can be enabled or disabled, crystal/
resonator connected between RA6 and
RA7
High-Speed Crystal/Resonator mode,
PLL always disabled, crystal/resonator
connected between RA6 and RA7
enabled or disabled, CLKO on RA6, port
function on RA7, the internal oscillator
block is used to derive both the primary
clock source and the postscaled internal
clock
enabled or disabled, port function on
RA6 and RA7, the internal oscillator
block is used to derive both the primary
clock source and the postscaled internal
clock
Internal Oscillator mode, PLL is always
disabled, CLKO on RA6, port function on
RA7, the output of the INTOSC
postscaler serves as both the postscaled
internal clock and the primary clock
source
Internal Oscillator mode, PLL is always
disabled, port function on RA6 and RA7,
the output of the INTOSC postscaler
serves as both the postscaled internal
clock and the primary clock source
OSCILLATOR MODES
Description
DS39775C-page 35