C8051F365-GM Silicon Laboratories Inc, C8051F365-GM Datasheet - Page 9

• Manufacturer Part Number: C8051F365-GM
• Description: IC 8051 MCU 32K FLASH 28-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F36xr

Specifications of C8051F365-GM

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 28-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F360DK
• Minimum Operating Temperature: - 40 C
• Package: 28QFN
• Device Core: 8051
• Family Name: C8051F36x
• Maximum Speed: 100 MHz
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1647

9. CIP-51 Microcontroller
10. Interrupt Handler
11. Multiply And Accumulate (MAC0)
12. Reset Sources
13. Flash Memory
14. Branch Target Cache
15. External Data Memory Interface and On-Chip XRAM
16. Oscillators
17. Port Input/Output
Figure 8.2. Comparator1 Functional Block Diagram ............................................... 71
Figure 8.3. Comparator Hysteresis Plot .................................................................. 72
Figure 9.1. CIP-51 Block Diagram .......................................................................... 81
Figure 9.2. Memory Map ......................................................................................... 86
Figure 9.3. SFR Page Stack .................................................................................... 89
Figure 9.4. SFR Page Stack While Using SFR Page 0x0F To Access OSCICN .... 90
Figure 9.5. SFR Page Stack After ADC0 Window Comparator Interrupt Occurs .... 91
Figure 9.6. SFR Page Stack Upon PCA Interrupt Occurring During an ADC0 ISR . 91
Figure 9.7. SFR Page Stack Upon Return From PCA Interrupt .............................. 92
Figure 9.8. SFR Page Stack Upon Return From ADC2 Window Interrupt .............. 93
Figure 11.1. MAC0 Block Diagram ........................................................................ 117
Figure 11.2. Integer Mode Data Representation ................................................... 118
Figure 11.3. Fractional Mode Data Representation ............................................... 118
Figure 11.4. MAC0 Pipeline ................................................................................... 119
Figure 12.1. Reset Sources ................................................................................... 128
Figure 12.2. Power-On and VDD Monitor Reset Timing ....................................... 129
Figure 13.1. Flash Program Memory Map ............................................................. 138
Figure 14.1. Branch Target Cache Data Flow ....................................................... 145
Figure 14.2. Branch Target Cache Organization ................................................... 146
Figure 14.3. Cache Lock Operation ....................................................................... 148
Figure 15.1. Multiplexed Configuration Example ................................................... 157
Figure 15.2. Non-multiplexed Configuration Example ........................................... 158
Figure 15.3. EMIF Operating Modes ..................................................................... 159
Figure 15.4. Non-multiplexed 16-bit MOVX Timing ............................................... 162
Figure 15.5. Non-multiplexed 8-bit MOVX without Bank Select Timing ................ 163
Figure 15.6. Non-multiplexed 8-bit MOVX with Bank Select Timing ..................... 164
Figure 15.7. Multiplexed 16-bit MOVX Timing ....................................................... 165
Figure 15.8. Multiplexed 8-bit MOVX without Bank Select Timing ........................ 166
Figure 15.9. Multiplexed 8-bit MOVX with Bank Select Timing ............................. 167
Figure 16.1. Oscillator Diagram ............................................................................. 169
Figure 16.2. 32.768 kHz External Crystal Example ............................................... 176
Figure 16.3. PLL Block Diagram ............................................................................ 178
Figure 17.1. Port I/O Functional Block Diagram (Port 0 through Port 3) ............... 183
Figure 17.2. Port I/O Cell Block Diagram .............................................................. 184
Figure 17.3. Crossbar Priority Decoder with No Pins Skipped .............................. 185
Figure 17.4. Crossbar Priority Decoder with Port Pins Skipped ............................ 186
C8051F360/1/2/3/4/5/6/7/8/9
Rev. 1.0
9