ATMEGA48PA-AU Atmel, ATMEGA48PA-AU Datasheet
ATMEGA48PA-AU
Specifications of ATMEGA48PA-AU
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ATMEGA48PA-AU Summary of contents
Page 1
... • Speed Grade: – MHz @ 1.8 - 5.5V • Low Power Consumption at 1 MHz, 1.8V, 25°C for ATmega48PA/88PA/168PA/328P: – Active Mode: 0.2 mA – Power-down Mode: 0.1 µA – Power-save Mode: 0.75 µA (Including 32 kHz RTC) ® 8-Bit Microcontroller ( compatible) ...
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... Pin Configurations Figure 1-1. Pinout ATmega48PA/88PA/168PA/328P TQFP Top View (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 2 GND 3 VCC 4 GND 5 VCC 6 (PCINT6/XTAL1/TOSC1) PB6 7 (PCINT7/XTAL2/TOSC2) PB7 8 28 MLF Top View (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 2 VCC 3 GND 4 (PCINT6/XTAL1/TOSC1) PB6 5 (PCINT7/XTAL2/TOSC2) PB7 6 (PCINT21/OC0B/T1) PD5 7 NOTE: Bottom pad should be soldered to ground. ...
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... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P ”System Clock and Clock Options” on page Table 28-3 on page ”Alternate Functions of Port B” on page 26 ...
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... In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels. 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P , even if the ADC is not used. If the ADC is used, it should be connected ”Alternate Functions of Port D” on page ...
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... Overview The ATmega48PA/88PA/168PA/328P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega48PA/88PA/168PA/328P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...
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... ATmega88PA, ATmega168PA and ATmega328P support a real Read-While-Write Self-Pro- gramming mechanism. There is a separate Boot Loader Section, and the SPM instruction can only execute from there. In ATmega48PA, there is no Read-While-Write support and no sepa- rate Boot Loader Section. The SPM instruction can execute from the entire Flash. ...
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... A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P 1. 7 ...
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... Reserved – (0xC7) Reserved – (0xC6) UDR0 (0xC5) UBRR0H (0xC4) UBRR0L (0xC3) Reserved – (0xC2) UCSR0C UMSEL01 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P Bit 6 Bit 5 Bit 4 Bit 3 – – – – – – – – – – – – – – – ...
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... ICR1L (0x85) TCNT1H (0x84) TCNT1L (0x83) Reserved – (0x82) TCCR1C FOC1A (0x81) TCCR1B ICNC1 (0x80) TCCR1A COM1A1 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P Bit 6 Bit 5 Bit 4 Bit 3 TXCIE0 UDRIE0 RXEN0 TXEN0 TXC0 UDRE0 FE0 DOR0 – – – – – – TWAM5 ...
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... COM0A1 0x23 (0x43) GTCCR TSM 0x22 (0x42) EEARH 0x21 (0x41) EEARL 0x20 (0x40) EEDR 0x1F (0x3F) EECR – 0x1E (0x3E) GPIOR0 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P Bit 6 Bit 5 Bit 4 – – – – ADC5D ADC4D ADC3D – – – REFS0 ADLAR – ...
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... Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega48PA/88PA/168PA/328P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used ...
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... Branch if T Flag Set BRTC k Branch if T Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P Description Rd ← ← Rdh:Rdl ← Rdh:Rdl + K Rd ← ← ← ← Rdh:Rdl ← Rdh:Rdl - K Rd ← Rd • ← Rd • ← ...
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... Rd Port OUT P, Rr Out Port PUSH Rr Push Register on Stack 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P Description then PC ← then PC ← I/O(P,b) ← 1 I/O(P,b) ← 0 Rd(n+1) ← Rd(n), Rd(0) ← 0 Rd(n) ← Rd(n+1), Rd(7) ← 0 Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Rd(n) ← ...
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... Pop Register from Stack MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P Description Rd ← STACK (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only Operation Flags #Clocks None None ...
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... Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 32M1-A 32-pad 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P (2) Ordering Code ATmega48PA-AU (4) ATmega48PA-MMH ATmega48PA-MU ATmega48PA-PU 306. Package Type (1) Package ...
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... Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 32M1-A 32-pad 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P (2) Ordering Code ATmega88PA-AU (4) ATmega88PA-MMH ...
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... Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 32M1-A 32-pad 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P (2) Ordering Code ATmega168PA-AU (4) ATmega168PA-MMH ...
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... Thin (1.0 mm) Plastic Quad Flat Package (TQFP) 28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 32M1-A 32-pad 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P (2) Ordering Code ATmega328P- AU ATmega328P- MU ATmega328P- PU 316 ...
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... This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P B PIN 1 IDENTIFIER TITLE 32A, 32-lead Body Size, 1 ...
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... 0.20 b 0.4 Ref BOTTOM VIEW (4x) The terminal # Laser-marked Feature. Note: Package Drawing Contact: packagedrawings@atmel.com 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P E 0. TITLE 28M1, 28-pad 1.0 mm Body, Lead Pitch 0.45 mm, 2.4 x 2.4 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) ...
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... Pin TOP VIEW Pin #1 Notch (0. BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. 2325 Orchard Parkway San Jose, CA 95131 R 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P TITLE 32M1-A, 32-pad 1.0 mm Body, Lead Pitch 0.50 mm, 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF) ...
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... A SEATING PLANE Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 8161DS–AVR–10/09 ATmega48PA/88PA/168PA/328P D PIN PLACES 0º ~ 15º REF eB TITLE 28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual ...
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... Errata 9.1 Errata ATmega48PA The revision letter in this section refers to the revision of the ATmega48PA device. 9.1.1 Rev known errata. 9.2 Errata ATmega88PA The revision letter in this section refers to the revision of the ATmega88PA device. 9.2.1 Rev known errata. 9.3 Errata ATmega168PA The revision letter in this section refers to the revision of the ATmega168PA device. ...
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... Inserted Ordering Information for ”ATmega328P” on page Inserted ”Errata ATmega328P” on page Editing updates. Updated ”Features” on page 1 for ATmega48PA and updated the book accordingly. Updated ”Overview” on page 5 included the Updated ”AVR Memories” on page 16 Figure 7-1 on page 17. ...
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... Interrupts” on page Inserted Typical characteristics for ”ATmega48PA Typical Characteristics” on page Updated figure names in Typical characteristics for istics” on page 351. Inserted ”ATmega48PA DC Characteristics” on page Updated Table 28-1 on page 317 Updated Table 28-7 on page 323 accuracy 4V 4V, ADC clock = 200 kHz. ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...