ATMEGA48PA-MU Atmel, ATMEGA48PA-MU Datasheet - Page 47

• Manufacturer Part Number: ATMEGA48PA-MU
• Description: MCU AVR 4KB FLASH IND 32QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA48PA-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Processor Series: ATMEGA48x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 6 Channel
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10. System Control and Reset
10.1
10.2
8271C–AVR–08/10
Resetting the AVR
Reset Sources
During reset, all I/O Registers are set to their initial values, and the program starts execution
from the Reset Vector. For ATmega168A/168PA/328/328P the instruction placed at the Reset
Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. For the
ATmega 48A/48PA and ATmega88A/88PA, the instruction placed at the Reset Vector must be
an RJMP – Relative Jump – instruction to the reset handling routine. If the program never
enables an interrupt source, the Interrupt Vectors are not used, and regular program code can
be placed at these locations. This is also the case if the Reset Vector is in the Application sec-
t i o n w h i l e t h e I n t e r r u p t V e c t o r s a r e i n t h e B o o t s e c t i o n o r v i c e v e r s a
(ATmega88A/88PA/168A/168PA/328/328P only). The circuit diagram in
shows the reset logic.
circuitry.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The time-out
period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-
ferent selections for the delay period are presented in
The ATmega48A/48PA/88A/88PA/168A/168PA/328/328P has four sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset
• External Reset. The MCU is reset when a low level is present on the RESET pin for longer than
• Watchdog System Reset. The MCU is reset when the Watchdog Timer period expires and the
• Brown-out Reset. The MCU is reset when the supply voltage V
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
threshold (V
the minimum pulse length.
Watchdog System Reset mode is enabled.
threshold (V
POT
BOT
).
) and the Brown-out Detector is enabled.
Table 28-12 on page 323
defines the electrical parameters of the reset
”Clock Sources” on page
CC
is below the Brown-out Reset
Figure 10-1 on page 48
27.
47