PIC16C712-20/P Microchip Technology, PIC16C712-20/P Datasheet - Page 64

• Manufacturer Part Number: PIC16C712-20/P
• Description: IC MCU OTP 1KX14 A/D PWM 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C712-20/P

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Number Of I /o: 13
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16C
• No. Of I/o's: 13
• Ram Memory Size: 128Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16C712/716
9.10.1
External interrupt on RB0/INT pin is edge triggered,
either rising if bit INTEDG (OPTION_REG<6>) is set,
or falling if the INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can wake-up the processor from Sleep, if bit INTE
was set prior to going into Sleep. The status of global
interrupt enable bit GIE decides whether or not the
processor branches to the interrupt vector following
wake-up. See Section 9.13 “Power-down Mode
(Sleep)” for details on Sleep mode.
9.10.2
An overflow (FFh
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 4.0 “Timer0 Module”)
9.10.3
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 3.2 “PORTB and the TRISB Register”)
EXAMPLE 9-1:
DS41106B-page 62
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
BCF
MOVF
MOVWF
:
:(ISR)
:
MOVF
MOVWF
SWAPF
MOVWF
SWAPF
SWAPF
on
INT INTERRUPT
TMR0 INTERRUPT
PORTB INTCON CHANGE
the
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
STATUS, IRP
FSR, W
FSR_TEMP
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
00h) in the TMR0 register will set
RB0/INT
SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
pin,
flag
;Copy W to TEMP register, could be bank one or zero
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
;Return to Bank 0
;Copy FSR to W
;Copy FSR from W to FSR_TEMP
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
bit
INTF
9.11
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt, (i.e., W register and STATUS
register). This will have to be implemented in software.
Example 9-1 stores and restores the W and STATUS
registers. The register, W_TEMP, must be defined in
each bank and must be defined at the same offset from
the bank base address (i.e., if W_TEMP is defined at
0x20 in bank 0, it must also be defined at 0xA0 in bank
1).
The example:
a)
b)
c)
d)
e)
f)
Stores the W register.
Stores the STATUS register in bank 0.
Stores the PCLATH register.
Executes the Interrupt Service Routine code
(User-generated).
Restores the STATUS register (and bank select
bit).
Restores the W and PCLATH registers.
Context Saving During Interrupts
© 2005 Microchip Technology Inc.