PIC12LC671-04I/SM Microchip Technology, PIC12LC671-04I/SM Datasheet - Page 65

• Manufacturer Part Number: PIC12LC671-04I/SM
• Description: IC MCU OTP 1KX14 LV A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12LC671-04I/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Processor Series: PIC12LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 8
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

9.7
The Watchdog Timer is a free running, on-chip RC
oscillator, which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEP instruction. Dur-
ing normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The WDT can be permanently
disabled
(Section 9.1).
9.7.1
The WDT has a nominal time-out period of 18 ms (with
no prescaler). The time-out periods vary with tempera-
ture, V
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
FIGURE 9-15: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 9-8:
Address
2007h
81h
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 9-1 for operation of these bits. Not all CP0 and CP1 bits are shown.
Note: PSA and PS<2:0> are bits in the OPTION register.
1999 Microchip Technology Inc.
DD
Watchdog Timer (WDT)
WDT PERIOD
and process variations from part to part (see
by
clearing
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Config. bits
OPTION
WDT Timer
Enable Bit
WDT
configuration
(1)
From TMR0 Clock Source
(Figure 7-5)
MCLRE
GPPU
Bit 7
bit
0
1
WDTE
INTEDG
PSA
Bit 6
CP1
M
U
X
T0CS
Bit 5
CP0
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out early and generating a premature
device RESET condition.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
9.7.2
It should also be taken into account that under worst
case conditions (V
max. WDT prescaler), it may take several seconds
before a WDT time-out occurs.
See Example 7-1 and Example 7-2 for changing pres-
caler between WDT and Timer0.
0
Note:
PWRTE
Time-out
8 - to - 1 MUX
MUX
T0SE
Bit 4
WDT
Postscaler
WDT PROGRAMMING CONSIDERATIONS
When the prescaler is assigned to the
WDT, always execute a CLRWDT instruction
before changing the prescale value, other-
wise a WDT reset may occur.
1
8
WDTE
Bit 3
PSA
DD
PSA
To TMR0 (Figure 7-5)
= Min., Temperature = Max., and
FOSC2
PIC12C67X
Bit 2
PS2
PS<2:0>
FOSC1
Bit 1
PS1
DS30561B-page 65
FOSC0
Bit 0
PS0