PIC16F818-I/SSTSL Microchip Technology, PIC16F818-I/SSTSL Datasheet - Page 99
![IC PIC MCU FLASH 1KX14 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16F818-I/SSTSL
Manufacturer Part Number
PIC16F818-I/SSTSL
Description
IC PIC MCU FLASH 1KX14 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(176 pages)
4.PIC16F818-ISO.pdf
(6 pages)
5.PIC16F818-ISO.pdf
(8 pages)
6.PIC16F818-ISO.pdf
(8 pages)
Specifications of PIC16F818-I/SSTSL
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC16F818-ISO PDF datasheet #5
- PIC16F818-ISO PDF datasheet #6
- Current page: 99 of 688
- Download datasheet (3Mb)
6.2.4
1997 Microchip Technology Inc.
Program Counter (PC)
The program counter (PC) specifies the address of the instruction to fetch for execution. The PC
is 13-bits wide. The low byte is called the PCL register. This register is readable and writable. The
high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly
readable or writable. All updates to the PCH register go through the PCLATH register.
Figure 6-2
loaded on a write to PCL (PCLATH<4:0>
a GOTO instruction (PCLATH<4:3>
CALL instruction (PCLATH<4:3>
Situation 4 shows how the PC is loaded during one of the return instructions where the PC
loaded (POPed) from the Top of Stack.
Figure 6-2: Loading of PC In Different Situations
Situation 1 - Instruction with PCL as destination
Situation 2 - GOTO Instruction
Situation 3 - CALL Instruction
Situation 4 - RETURN, RETFIE, or RETLW Instruction
Section 6. Memory Organization
PC
PC
PC
PC
shows the four situations for the loading of the PC. Situation 1 shows how the PC is
Note: PCLATH is never updated with the contents of PCH.
12
12 11 10
12 11 10
12 11 10
2
2
5
PCH
PCLATH<4:3>
PCH
PCLATH<4:3>
PCH
PCH
PCLATH
PCLATH
PCLATH
PCLATH<4:0>
8
8
8
PCLATH
8
7
7
7
7
PCL
PCL
PCL
PCL
PCH), with the PC loaded (PUSHed) onto the Top of Stack.
PCH). Situation 3 shows how the PC is loaded during a
11
11
11
PCH). Situation 2 shows how the PC is loaded during
8
ALU result
0
0
0
0
13
13
Opcode <10:0>
Opcode <10:0>
Opcode <10:0>
STACK (13-bits x 8)
STACK (13-bits x 8)
STACK (13-bits x 8)
STACK (13-bits x 8)
Top of STACK
Top of STACK
Top of STACK
Top of STACK
DS31006A-page 6-5
6
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