PIC12C672-10E/SM Microchip Technology, PIC12C672-10E/SM Datasheet - Page 91
PIC12C672-10E/SM
Manufacturer Part Number
PIC12C672-10E/SM
Description
IC MCU OTP 2KX14 A/D 8-SOIJ
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(14 pages)
Specifications of PIC12C672-10E/SM
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
For Use With
XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC12C672-10E/SM
Manufacturer:
MICROCH
Quantity:
20 000
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- Download datasheet (3Mb)
5.8
1997 Microchip Technology Inc.
PCON Register
bit 7
bit 6:3
bit 2
bit 1
bit 0
The Power Control (PCON) register contains flag bit(s), that together with the TO and PD bits,
allows the user to differentiate between the device resets.
Register 5-3: PCON Register
bit 7
MPEEN: Memory Parity Error Circuitry Status bit
This bit reflects the value of the MPEEN configuration bit.
Unimplemented: Read as '0'
PER: Memory Parity Error Reset Status bit
1 = No error occurred
0 = A program memory fetch parity error occurred
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend
R = Readable bit
U = Unimplemented bit, read as ‘0’
MPEEN
Note 1: BOR is unknown on Power-on Reset. It must then be set by the user and checked
Note 2: It is recommended that the POR bit be cleared after a power-on reset has been
(must be set in software after a Power-on Reset occurs)
R-u
on subsequent resets to see if BOR is clear, indicating a brown-out has occurred.
The BOR status bit is a don't care and is not necessarily predictable if the brown-out
circuit is disabled (by clearing the BODEN bit in the Configuration word).
detected, so that subsequent power-on resets may be detected.
U-0
—
W = Writable bit
U-0
—
Section 5. CPU and ALU
U-0
—
- n = Value at POR reset
U-0
—
R/W-0
PER
R/W-0
POR
DS31005A-page 5-9
bit 0
R/W-0
BOR
5
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