PIC18F66J11T-I/PT Microchip Technology, PIC18F66J11T-I/PT Datasheet - Page 2
![IC PIC MCU FLASH 32KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F66J11T-I/PT
Manufacturer Part Number
PIC18F66J11T-I/PT
Description
IC PIC MCU FLASH 32KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.DV164136.pdf
(448 pages)
3.DV164136.pdf
(4 pages)
4.PIC18F63J11-IPT.pdf
(36 pages)
5.PIC18F66J11-IPT.pdf
(4 pages)
6.PIC18F66J11-IPT.pdf
(4 pages)
7.PIC18F66J11-IPT.pdf
(20 pages)
Specifications of PIC18F66J11T-I/PT
Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Type
FLASH
Ram Size
3930 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
No. Of I/o's
52
Ram Memory Size
3930Byte
Cpu Speed
48MHz
No. Of Timers
5
No. Of
RoHS Compliant
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3904 B
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
52
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162091 - HEADER MPLAB ICD2 18F87J11 64/80MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18F66J11T-I/PTTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F66J11T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F87J11 FAMILY
TABLE 2:
DS80495D-page 2
MSSPx
Oscillator
Configuration
Voltage
Regulator
SRAM
Low-Voltage
Detect
MSSPx
EUSART
Note 1:
Module
Only those issues indicated in the last column apply to the current silicon revision.
I
Reception
PLL
V
Read/Write
LVDSTAT
I
mode
Synchronous
Mode
2
2
SILICON ISSUE SUMMARY
DDCORE
C™ Slave
C™ Master
Feature
Num
Item
1.
2.
3.
4.
5.
6.
7.
When configured for I
MSSPx module may not receive the correct
data if the SSPxBUF register is not read within a
window after an SSPxIF interrupt occurs.
When Phase Lock Loop (PLL) is enabled, if the
PLL input frequency is higher than 8 MHz, there
may be problems accessing the RAM.
If V
while the on-chip core voltage regulator is
enabled and operating in Voltage Tracking
mode, the REGSLP bit (WDTCON <7>) will be
automatically cleared.
Any read or write access to SRAM will increase
the current consumption of the device – varying
with how often the SRAM is accessed.
The LVDSTAT V
implemented in the cited revision of silicon.
In Master mode, the first clock may become
narrower than the configuration width if the
slave performs a clock stretch and release.
The TRMT bit may not indicate when the TSR
register is empty.
DDCORE
drops below approximately 2.45V
Issue Summary
DDCORE
2
C slave reception, the
status bit is not
A1
X
X
X
X
X
X
X
2011 Microchip Technology Inc.
Affected Revisions
A2
X
X
X
X
A4
X
X
X
A5
X
X
X
A6
X
X
X
(1)
C1
X
X
X