ATTINY461-15MZ Atmel, ATTINY461-15MZ Datasheet - Page 169

• Manufacturer Part Number: ATTINY461-15MZ
• Description: MCU AVR 4K FLASH 15MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY461-15MZ

• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.4.4
21.5
21.5.1
7753F–AVR–01/11
Register Description
Programming Time for Flash when Using SPM
SPMCSR – Store Program Memory Control and Status Register
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
2. Keep the AVR core in Power-down sleep mode during periods of low V
The calibrated RC Oscillator is used to time Flash accesses.
gramming time for Flash accesses from the CPU.
Table 21-1.
Note:
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Program memory operations.
• Bits 7:6 – Res: Reserved Bits
These bits are reserved bits in the ATtiny261/461/861 and always read as zero.
• Bit 5 – SIGRD: Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three
clock cycles will read a byte from the signature row into the destination register for details. An
SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect.
• Bit 4 – CTPB: Clear Temporary Page Buffer
If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be
cleared and the data will be lost.
• Bit 3 – RFLB: Read Fuse and Lock Bits
An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register,
will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destina-
tion register. See
Bit
0x37 (0x57)
Read/Write
Initial Value
Flash write (Page Erase, Page Write, and
write Lock bits by SPM)
This can be done by enabling the internal Brown-out Detector (BOD) if the operating volt-
age matches the detection level. If not, an external low V
used. If a reset occurs while a write operation is in progress, the write operation will be
completed provided that the power supply voltage is sufficient.
vent the CPU from attempting to decode and execute instructions, effectively protecting
the SPMCSR Register and thus the Flash from unintentional writes.
1. Minimum and maximum programming time is per individual operation.
7
–
R
0
SPM Programming Time
Symbol
“EEPROM Write Prevents Writing to SPMCSR” on page 168
6
–
R
0
5
SIGRD
R
0
ATtiny261/ATtiny461/ATtiny861
(1)
4
CTPB
R/W
0
Min Programming Time
3
RFLB
R/W
0
3.7 ms
CC
2
PGWRT
R/W
0
Table 21-1
reset protection circuit can be
1
PGERS
R/W
0
Max Programming Time
shows the typical pro-
CC
. This will pre-
0
SPMEN
R/W
0
for details.
4.5 ms
SPMCSR
169