PIC18F25J11-I/SS Microchip Technology, PIC18F25J11-I/SS Datasheet - Page 4

• Manufacturer Part Number: PIC18F25J11-I/SS
• Description: IC PIC MCU FLASH 32K 2V 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F25J11-I/SS

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180023
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F46J11 FAMILY
3. Module: Enhanced Universal
EXAMPLE 1:
4. Module: 10-Bit Analog-to-Digital
TABLE 3:
DS80435H-page 4
;Initial conditions: SPEN = 0 (module disabled)
;To re-enable the module:
;Re-Initialize TXSTAx, BAUDCONx, SPBRGx, SPBRGHx registers (if needed)
;Re-Initialize RCSTAx register (if needed), but do not set SPEN = 1 yet
;Now enable the module, but add a 2-Tcy delay before executing any two-cycle
;instructions
bsf
nop
nop
In rare situations when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (SPEN bit
• The EUSART is re-enabled (RCSTAx<7> = 1)
• A two-cycle instruction is executed immediately
When the A/D conversion clock select bits are set
for F
Linearity Error (E
tial Linearity Error (E
exceed data sheet specifications.
Work around
Select one of the alternate A/D clock sources
shown in
Affected Silicon Revisions
ADCON1<2:0>
A2
ADCS<2:0>
(RCSTAx<7>) = 0)
after setting SPEN, CREN or TXEN = 1
X
OSC
110
101
100
011
010
001
RCSTA1, SPEN
A4
X
/2 (ADCON1<2:0> = 000), the Integral
Table
Synchronous Asynchronous
Receiver Transmitter (EUSART)
Converter (A/D)
ALTERNATE ADC SETTINGS
RE-ENABLING A EUSART MODULE
3.
IL
), parameter (A03) and Differen-
DL
), parameter (A04), may
Clock Setting
F
F
F
F
F
OSC
OSC
OSC
OSC
OSC
F
;or RCSTA2 if EUSART2
;1 Tcy delay
;1 Tcy delay (two total)
RC
/64
/16
/32
/4
/8
5. Module: Parallel Master Port (PMP)
Work around
Add a 2 T
enables the EUSART module (sets SPEN, CREN
or TXEN = 1).
See
Affected Silicon Revisions
When
(PMMODEH<1:0> = 00 and PMPEN = 1), the data
bus (PMD<7:0>) may not work correctly. Incorrect
data could be captured in the PMDIN1L register.
When
(PMMODEH<1:0> = 10 and PMPEN = 1), clearing
a PMEx bit to disable a PMP address line also
disables the corresponding PMDx data bus line.
Work around
None.
Affected Silicon Revisions
A2
A2
X
X
Example
A4
A4
configured
X
configured
CY
delay after any instruction that re-
1.
 2010 Microchip Technology Inc.
for
for
Parallel
Parallel
Master
Slave
Port
Port