ATMEGA8A-PU Atmel, ATMEGA8A-PU Datasheet - Page 48

• Manufacturer Part Number: ATMEGA8A-PU
• Description: MCU AVR 8K FLASH 16MHZ 28-PDIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Package: 28PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.1.1
11.2
11.2.1
8159D–AVR–02/11
Register Description
Moving Interrupts Between Application and Boot Space
GICR – General Interrupt Control Register
When the BOOTRST Fuse is programmed, the boot section size set to 2K bytes, and the IVSEL
bit in the GICR Register is set before any interrupts are enabled, the most typical and general
program setup for the Reset and Interrupt Vector Addresses is:
The General Interrupt Control Register controls the placement of the Interrupt Vector table.
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash
memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot
Loader section of the Flash. The actual address of the start of the boot Flash section is deter-
mined by the BOOTSZ Fuses. Refer to the section
Self-Programming” on page 212
tables, a special write procedure must be followed to change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status
Register is unaffected by the automatic disabling.
Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro-
grammed, interrupts are disabled while executing from the Application section. If Interrupt
Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts
are disabled while executing from the Boot Loader section. Refer to the section
Support – Read-While-Write Self-Programming” on page 212
Bit
Read/Write
Initial Value
AddressLabels
;
.org $c00
$c00
$c01
$c02
:.
$c12
$c13
$c14
$c15
$c16
$c17
$c18
RESET: ldi
INT1
R/W
7
0
rjmp
rjmp
rjmp
:.
rjmp
out
ldi
out
sei
<instr>
Code
INT0
R/W
6
0
RESET
EXT_INT0
EXT_INT1
:. ;
SPM_RDY
SPH,r16
r16,low(RAMEND)
SPL,r16
xxx
r16,high(RAMEND); Main program start
for details. To avoid unintentional changes of Interrupt Vector
R
5
–
0
R
4
–
0
Comments
; Reset handler
; IRQ0 Handler
; IRQ1 Handler
; Store Program Memory Ready Handler
; Set Stack Pointer to top of RAM
; Enable interrupts
“Boot Loader Support – Read-While-Write
R
3
–
0
for details on Boot Lock Bits.
R
2
–
0
IVSEL
R/W
1
0
ATmega8A
IVCE
R/W
0
0
“Boot Loader
GICR
48