AT90CAN32-16AUR Atmel, AT90CAN32-16AUR Datasheet
AT90CAN32-16AUR
Specifications of AT90CAN32-16AUR
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AT90CAN32-16AUR Summary of contents
Page 1
... Selectable Boot Size: 1K Bytes, 2K Bytes, 4K Bytes or 8K Bytes • In-System Programming by On-Chip Boot Program (CAN, UART, ...) • True Read-While-Write Operation – 1K/2K/4K Bytes EEPROM (Endurance: 100,000 Write/Erase Cycles) (AT90CAN32/64/128) – 2K/4K/4K Bytes Internal SRAM (AT90CAN32/64/128) – 64K Bytes Optional External Memory Space – ...
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... AT90CAN128 1.2 Part Description The AT90CAN32/64/128 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90CAN32/64/128 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ...
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... Atmel AT90CAN32/64/128 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90CAN32/64/128 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emula- tors, and evaluation kits. ...
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... INSTRUCTION SCAN REGISTER PROGRAMMING INSTRUCTION LOGIC DECODER CONTROL LINES USART0 DATA REGISTER PORTE REG. PORTE PORTE DRIVERS PE7 - PE0 AT90CAN32/64/128 4 PA7 - PA0 PORTA DRIVERS DATA DIR. DATA REGISTER DATA DIR. PORTA REG. PORTA POR - BOD RESET INTERNAL OSCILLATOR WATCHDOG STACK POINTER ...
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... Pin Configurations Figure 1-2. Pinout AT90CAN32/64/128 - TQFP ( (RXD0 / PDI) PE0 2 (TXD0 / PDO) PE1 3 (XCK0 / AIN0) PE2 4 (OC3A / AIN1) PE3 5 (OC3B / INT4) PE4 6 (OC3C / INT5) PE5 7 (T3 / INT6) PE6 8 (ICP3 / INT7) PE7 9 (SS) PB0 10 (SCK) PB1 11 (MOSI) PB2 12 (MISO) PB3 13 (OC2A) PB4 ...
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... Figure 1-3. Pinout AT90CAN32/64/128 - QFN (1) NC (RXD0 / PDI) PE0 (TXD0 / PDO) PE1 (XCK0 / AIN0) PE2 (OC3A / AIN1) PE3 (OC3B / INT4) PE4 (OC3C / INT5) PE5 (T3 / INT6) PE6 (ICP3 / INT7) PE7 (SS) PB0 (SCK) PB1 (MOSI) PB2 (MISO) PB3 (OC2A) PB4 (OC1A) PB5 (OC1B) PB6 ...
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... As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the AT90CAN32/64/128 as listed on page 1 ...
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... Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset. The minimum pulse length is given in characteristics. Shorter pulses are not guaranteed to generate a reset. The I/O ports of the AVR are immediately reset to their initial state even if the clock is not running. The clock is needed to reset the rest of the AT90CAN32/64/128. 1.6.11 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit ...
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... The program memory is In-System Reprogrammable Flash memory. 7679H–CAN–08/08 Block Diagram of the AVR Architecture Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines AT90CAN32/64/128 Data Bus 8-bit Status and Control Interrupt Unit General Purpose SPI Registrers Unit Watchdog ...
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... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the AT90CAN32/64/128 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
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... Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 7679H–CAN–08/ R/W R/W R/W R ⊕ V AT90CAN32/64/128 SREG R/W R/W R/W R ...
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... The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in AT90CAN32/64/128 12 shows the structure of the 32 general purpose working registers in the CPU. ...
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... Bit 0 – RAMPZ0: Extended RAM Page Z-pointer The RAMPZ Register is normally used to select which 64K RAM Page is accessed by the Z- pointer. As the AT90CAN32/64/128 does not support more than 64K of SRAM memory, this reg- ister is used only to select which page in the program memory is accessed when the ELPM/SPM instruction is used ...
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... No internal clock division is used. Figure 3-5 vard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 3-5. AT90CAN32/64/128 ...
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... Single Cycle ALU Operation T1 clk CPU Total Execution Register Operands Fetch ALU Operation Execute Result Write Back for details. “Boot Loader Support – Read-While-Write Self-Programming” on page AT90CAN32/64/128 T2 T3 “Memory Program- “Interrupts” on page 60. The list also “Interrupts” on page 60 for more information ...
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... C Code Example _SEI(); _SLEEP(); /* note: will enter sleep before any pending interrupt(s) */ AT90CAN32/64/128 16 r16, SREG ; store SREG value ; disable interrupts during timed sequence EECR, EEMWE ; start EEPROM write ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 7679H–CAN–08/08 AT90CAN32/64/128 17 ...
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... Memories This section describes the different memories in the AT90CAN32/64/128. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the AT90CAN32/64/128 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. ...
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... I/O memory, then 160 locations of Extended I/O memory, and the next locations address the internal data SRAM (see “ISRAM size”). An optional external data SRAM can be used with the AT90CAN32/64/128. This SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM ...
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... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the “ISRAM size” bytes of internal data SRAM in the AT90CAN32/64/128 are all accessible through all these addressing modes. The Register File is described in ter File” ...
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... External SRAM (XMem size) On-chip Data SRAM Access Cycles T1 clk CPU Address Compute Address Data WR Data RD Memory Access Instruction AT90CAN32/64/128 0x0000 - 0x001F 0x0020 - 0x005F 0x0060 - 0x00FF ISRAM start ISRAM end XMem start 0xFFFF cycles as described in Figure CPU T2 T3 Address valid Next Instruction 4-3 ...
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... The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. – AT90CAN32: EEAR11 & EEAR10 exist as register bit but they are not used for – AT90CAN64: EEAR11 exists as register bit but it is not used for addressing. ...
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... Initial Value • Bits 7..4 – Reserved Bits These bits are reserved bits in the AT90CAN32/64/128 and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt ...
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... EEPROM, nor to change the EEAR Register. The calibrated Oscillator is used to time the EEPROM accesses. gramming time for EEPROM access from the CPU. Table 4-2. Symbol EEPROM write (from CPU) AT90CAN32/64/128 24 EEPROM Programming Time. Number of Calibrated RC Oscillator Cycles 67 584 for details about Boot ...
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... Start eeprom write by setting EEWE sbi EECR,EEWE ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE)); /* Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); AT90CAN32/64/128 25 ...
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... Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low V be used reset occurs while a write operation is in progress, the write operation will be com- pleted provided that the power supply voltage is sufficient. AT90CAN32/64/128 26 EECR,EEWE EEPROM_read ...
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... When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The AT90CAN32/64/128 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions ...
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... Note that when the XMEM inter- face is disabled, the address space above the internal SRAM boundary is not mapped into the internal SRAM. octal latch (typically “74x573” or equivalent) which is transparent when G is high. AT90CAN32/64/128 28 External Memory with Sector Select Internal memory ...
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... The most important parameters are the access time for the external memory compared to the set-up requirement of the AT90CAN32/64/128. The access time for the Exter- nal Memory is defined to be the time from receiving the chip select/address until the data of this 7679H– ...
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... The skew between the internal and external clock (XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Conse- quently, the XMEM interface is not suited for synchronous operation. Figure 4-6. Note: Figure 4-7. AT90CAN32/64/128 30 through Table 26-14). The different wait-states are set up in software addi- Table 26-7 ...
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... Address DA7:0 (XMBK = 1) Prev. data Address RD 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal or external). AT90CAN32/64/128 Address XX Data Data Data ...
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... SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address space is treated as one sector. When the entire SRAM address space is configured as one sec- tor, the wait-states are configured by the SRW11 and SRW10 bits. Table 4-3. SRL2 Note: AT90CAN32/64/128 SRE SRL2 SRL1 SRL0 R/W R/W R/W R/W ...
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... For further details of the timing and wait-states of the External Memory Interface, see Figures 4-6 through Figures 4-9 for how the setting of the SRW bits affects the timing XMBK – – – R AT90CAN32/64/128 – XMM2 XMM1 XMM0 XMCRB R R/W R/W R Table 4-5 ...
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... KB memory will appear as one linear 32 KB address space from “XMem start” to “XMem start + 0x8000”. This is illustrated in Figure 4-10. Address Map with 32 KB External Memory AT90CAN32/64/128 34 Port C Pins Released as Normal Port Pins when the External Memory is Enabled ...
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... PC7:5 for external memory ldi r16, (0<<XMM1)|(0<<XMM0) XMCRB, r16 sts ; store 0x55 to address (OFFSET + external memory ldi r16, 0x55 sts 0x0001+OFFSET, r16 (1) 1. The example code assumes that the part specific header file is included. AT90CAN32/64/128 Figure 4-4, only 35 ...
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... General Purpose I/O Registers The AT90CAN32/64/128 contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags. The General Purpose I/O Register 0, within the address range 0x00 - 0x1F, is directly bit-acces- sible using the SBI, CBI, SBIS, and SBIC instructions ...
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... Controller Modules CLKO CKOUT Fuse Multiplexer Timer/Counter2 Timer/Counter2 External Clock Oscillator TOSC1 TOSC2 is halted, enabling TWI address reception in all sleep modes. I/O AT90CAN32/64/128 “Power Management and ADC CPU Core clk ADC clk clk AVR Clock I/O CPU Control Unit clk clk ...
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... For all fuses “1” means unprogrammed while “0” means programmed. 384. Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out ( (1) CKSEL3..0 1111 - 1000 0111 - 0100 0010 0000 0011, 0001 “AT90CAN32/64/128 = 3.0V) Number of Cycles CC 4 (4,096 64K (65,536) Table 5-2. The 7679H–CAN–08/08 ...
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... Crystal Oscillator Connections Crystal Oscillator Operating Modes Frequency Range (MHz) (1) 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 16.0 1. This option should not be used with crystals, only with ceramic resonators. AT90CAN32/64/128 Figure 5-2. Either a quartz crystal XTAL2 C1 XTAL1 GND Recommended Range for Capacitors C1 and ...
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... Oscillator must be selected by setting the CKSEL Fuses to “0100”, “0101”, “0110”, or “0111”. The crystal should be connected as shown in Figure 5-3. 12-22 pF capacitors may be necessary if the parasitic impedance (pads, wires & PCB) is very low. AT90CAN32/64/128 40 Start-up Times for the Oscillator Clock Selection Start-up Time from SUT1..0 ...
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... This clock may be selected as the system clock by pro- and temperature. When this Oscillator is used as the chip clock, the Watchdog Oscil- CC Internal Calibrated RC Oscillator Operating Modes CKSEL3..0 0010 1. The device is shipped with this option selected. AT90CAN32/64/128 Table 5-6. = 5.0V) Recommended Usage CC Fast rising power or BOD enabled ...
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... External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in 5-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. AT90CAN32/64/128 42 Start-up times for the internal calibrated RC Oscillator clock selection Start-up Time from Power- ...
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... Signal External Clock Frequency Frequency Range MHz Start-up Times for the External Clock Selection Start-up Time from Power- Additional Delay from down and Power-save Reset ( AT90CAN32/64/128 XTAL2 XTAL1 GND Recommended Usage = 5.0V BOD enabled 4.1 ms Fast rising power Slowly rising power Reserved “ ...
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... System Clock Prescaler The AT90CAN32/64/128 system clock can be divided by setting the Clock Prescaler Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
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... The frequency of the asynchronous clock must be lower than 1/4th of the frequency of the scaled down Source clock. Otherwise, interrupts may be lost, and accessing the Timer/Counter2 regis- ters may fail. AT90CAN32/64/128 Clock Division Factor 128 0 256 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved ...
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... The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s AT90CAN32/64/128 46 Table 6-1 presents the different clock systems in the AT90CAN32/64/128, and their – ...
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... Power-save Mode When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power- save mode. This mode is identical to Power-down, with one exception: 7679H–CAN–08/08 AT90CAN32/64/128 and clk , while allowing the other clocks to run. CPU FLASH ...
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... If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis- abled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to 273 for details on ADC operation. AT90CAN32/64/128 48 Oscillators Main Timer ...
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... Digital CC “Digital Input Disable Register 1 – DIDR1” on page 272 for details. AT90CAN32/64/128 for details on how to configure the Analog “Brown-out Detection” on page 54 ) are stopped, the input buffers of the device will and “ ...
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... Note that the TDI pin for the next device in the scan chain con- tains a pull-up that avoids this problem. Writing the JTD bit in the MCUCR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface. AT90CAN32/64/128 50 7679H–CAN–08/08 ...
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... Reset Sources The AT90CAN32/64/128 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...
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... POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is properly reset from Power- started from V voltage invokes the delay counter, which determines how long the device is kept in RESET after AT90CAN32/64/128 52 Reset Logic Power-on Reset Circuit ...
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... External Reset is required. POR CCRR Table 7-1) will generate a reset, even if the clock is not running. – on its positive edge, the delay counter starts the MCU after RST – has expired. TOUT AT90CAN32/64/128 CC V CCRR V RST t TOUT decreases below ...
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... Figure 7-4. 7.1.5 Brown-out Detection AT90CAN32/64/128 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection ...
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... MCU after the Time-out period t given in Table 7-3. BOD Brown-out Reset During Operation V CC RESET TIME-OUT INTERNAL RESET for details on operation of the Watchdog Timer. Watchdog Reset During Operation CC AT90CAN32/64/128 V BOT+ V BOT- t TOUT CK has TOUT . Refer to TOUT 55 ...
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... Internal Voltage Reference AT90CAN32/64/128 features an internal bandgap reference. This reference is used for Brown- out Detection, and it can be used as an input to the Analog Comparator or the ADC. 7.2.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used ...
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... Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the AT90CAN32/64/128 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse WDTON as shown in Table 7-5 ...
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... Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0 The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch- dog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 7-6. WDP2 AT90CAN32/64/128 – – – WDCE R/W ...
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... WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) sts WDTCR, r16 ret (1) /* Write logical one to WDCE and WDE */ WDTCR = (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; 1. The example code assumes that the part specific header file is included. AT90CAN32/64/128 59 ...
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... Interrupts AT90CAN32/64/128. For a general explanation of the AVR interrupt handling, refer to and Interrupt Handling” on page 8.1 Interrupt Vectors in AT90CAN32/64/128 Table 8-1. Vector No AT90CAN32/64/128 60 15. Reset and Interrupt Vectors Program Source Interrupt Definition (1) Address External Pin, Power-on Reset, Brown-out Reset, (2) 0x0000 RESET ...
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... Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 8-2. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in AT90CAN32/64/128 is: ;Address 0x0000 0x0002 0x0004 0x0006 ...
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... IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: ;Address Labels 0x0000 0x0001 0x0002 0x0003 AT90CAN32/64/128 62 jmp TIM2_COMP ; Timer2 Compare Handler jmp TIM2_OVF ; Timer2 Overflow Handler jmp TIM1_CAPT ...
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... RESET: ldi r16,high(RAMEND) ; Main program start out SPH,r16 ldi r16,low(RAMEND) out SPL,r16 sei <instr> xxx AT90CAN32/64/128 ; Enable interrupts ; IRQ0 Handler ; PCINT0 Handler ; ; Store Program Memory Ready Handler Comments ; IRQ0 Handler ; PCINT0 Handler ; ; Store Program Memory Ready Handler ; Set Stack Pointer to top of RAM ...
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... Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: AT90CAN32/64/128 ...
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... MCUCR mov r17, r16 ; Enable change of Interrupt Vectors ori r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to Boot Flash section ori r17, (1<<IVSEL) out MCUCR, r17 ret uchar temp; temp = MCUCR; MCUCR = temp | (1<<IVCE); MCUCR = temp | (1<<IVSEL); AT90CAN32/64/128 65 ...
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... Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. AT90CAN32/64/128 66 “Electrical Characteristics (1)” on page 365 I/O Pin Equivalent Schematic ...
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... I/O CLOCK I/O 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. 89, the DDxn bits are accessed at the DDRx I/O address, the AT90CAN32/64/128 Figure 9 DDxn Q CLR ...
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... This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. gram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted t AT90CAN32/64/128 68 summarizes the control signals for the pin value. Port Pin Configurations ...
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... The out instruction sets the “SYNC LATCH” signal at the positive edge of through the synchronizer is 1 system clock period. pd Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK r16 INSTRUCTIONS out PORTx, r16 SYNC LATCH PINxn r17 AT90CAN32/64/128 XXX in r17, PINx 0x00 t pd, max t pd, min 0xFF nop in r17, PINx ...
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... If a logic high level (“one”) is present on an Asynchronous External Interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the AT90CAN32/64/128 70 (1) r16, (1< ...
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... The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. 7679H–CAN–08/08 AT90CAN32/64/128 or GND is not rec- CC Figure 9-5 ...
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... Figure 9-5. Note: Table 9-2 Figure 9-5 internally in the modules having the alternate function. AT90CAN32/64/128 72 (1) Alternate Port Functions PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn PVOVxn 1 Pxn 0 DIEOExn DIEOVxn 1 SLEEP 0 PUOExn: Pxn PULL-UP OVERRIDE ENABLE PUOVxn: Pxn PULL-UP OVERRIDE VALUE ...
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... This is the Analog Input/output to/from alternate functions. The Analog signal is connected directly to the pad, and can be used bi- Input/Output directionally JTD – – PUD R R AT90CAN32/64/128 – – IVSEL IVCE MCUCR R R R/W R ...
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... AD2, External memory interface address 2 and Data 2. • AD1 – Port A, Bit 1 AD1, External memory interface address 1 and Data 1. • AD0 – Port A, Bit 0 AD0, External memory interface address 0 and Data 0. AT90CAN32/64/128 74 Port A Pins Alternate Functions Port Pin Alternate Function PA7 ...
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... D3 A2 • ADA OUTPUT • WR OUTPUT • INPUT D2 INPUT – – 1. ADA is short for ADdress Active and represents the time when address is output. See nal Memory Interface” on page 27 AT90CAN32/64/128 PA5/AD5 SRE • (1) (1) + WR) (ADA + WR) 0 SRE WR + ADA SRE (1) ( • ADA + D5 OUTPUT • ...
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... DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB3. When the pin is forced input, the pull-up can still be controlled by the PORTB3 bit. • MOSI – Port B, Bit 2 AT90CAN32/64/128 76 Port B Pins Alternate Functions Alternate Functions ...
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... Overriding Signals for Alternate Functions in PB7..PB4 PB7/OC0A/OC1C PB6/OC1B OC0A/OC1C OC1B ENABLE (1) ENABLE (1) OC0A/OC1C OC1B – – – – 1. See “Output Compare Modulator - OCM” on page 165 AT90CAN32/64/128 PB5/OC1A PB4/OC2A OC1A ENABLE OC2A ENABLE OC1A OC2A – – – – for details. 77 ...
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... CLKO, Divided System Clock: The divided system clock can be output on the PC7 pin. The divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTC7 and DDC7 settings. It will also be output during reset. AT90CAN32/64/128 78 Overriding Signals for Alternate Functions in PB3..PB0 ...
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... CKOUT ) + A14 (1) (CLKO • CKOUT ) – – – – 1. CKOUT is one if the CKOUT Fuse is programmed AT90CAN32/64/128 PC5/A13 PC4/A12 SRE • (XMM<3) SRE • (XMM< SRE • (XMM<3) SRE • (XMM< SRE • (XMM<3) SRE • (XMM<4) A13 A12 ...
Page 80
... DDD6. When the CAN forces this pin input, the pull-up can still be controlled by the PORTD6 bit. T1, Timer/Counter1 counter source. • TXCAN/XCK1 – Port D, Bit 5 AT90CAN32/64/128 80 Overriding Signals for Alternate Functions in PC3..PC0 PC3/A11 PC2/A10 SRE • ...
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... Two-wire Serial Interface, pin PD0 is disconnected from the port and becomes the Serial Clock I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to sup- press spikes shorter than the input signal, and the pin is driven by an open drain driver with slew-rate limitation. 7679H–CAN–08/08 AT90CAN32/64/128 81 ...
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... Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: AT90CAN32/64/128 82 and Table 9-14 relates the alternate functions of Port D to the overriding signals Figure 9-5 on page 72. Overriding Signals for Alternate Functions PD7..PD4 PD7/T0 PD6/T1/RXCAN 0 RXCANEN 0 PORTD6 • PUD ...
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... INT4/OC3B (External Interrupt4 Input or Output Compare and PWM Output B for Timer/Counter3) AIN1/OC3A (Analog Comparator Negative Input or Output Compare and PWM Output A for Timer/Counter3) AIN0/XCK0 (Analog Comparator Positive Input or USART0 external clock input/output) PDO/TXD0 (Programming Data Output or UART0 Transmit Pin) PDI/RXD0 (Programming Data Input or UART0 Receive Pin) AT90CAN32/64/128 Table 9-15. 83 ...
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... Synchronous mode. • PDO/TXD0 – Port E, Bit 1 PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line for the AT90CAN32/64/128. TXD0, UART0 Transmit pin. • PDI/RXD0 – Port E, Bit 0 PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pin is used as data input line for the AT90CAN32/64/128 ...
Page 85
... ADC6/TDO (ADC input channel 6 or JTAG Data Output) ADC5/TMS (ADC input channel 5 or JTAG mode Select) ADC4/TCK (ADC input channel 4 or JTAG ClocK) ADC3 (ADC input channel 3) ADC2 (ADC input channel 2) ADC1 (ADC input channel 1) ADC0 (ADC input channel 0) AT90CAN32/64/128 PE1/PDO/TXD0 TXEN0 0 TXEN0 1 TXEN0 ...
Page 86
... ADC3, Analog to Digital Converter, input channel 3. • ADC2 – Port F, Bit 2 ADC2, Analog to Digital Converter, input channel 2. • ADC1 – Port F, Bit 1 ADC1, Analog to Digital Converter, input channel 1. • ADC0 – Port F, Bit 0 ADC0, Analog to Digital Converter, input channel 0. AT90CAN32/64/128 7679H–CAN–08/08 ...
Page 87
... ADC6 INPUT Overriding Signals for Alternate Functions in PF3..PF0 PF3/ADC3 PF2/ADC2 ADC3D ADC2D 0 0 – – ADC3 INPUT ADC2 INPUT AT90CAN32/64/128 PF5/ADC5/TMS PF4/ADC4/TCK JTAGEN JTAGEN JTAGEN JTAGEN JTAGEN JTAGEN 0 0 JTAGEN JTAGEN JTAGEN + JTAGEN + ADC5D ADC4D JTAGEN JTAGEN TMS TCK ADC5 INPUT ...
Page 88
... ALE is the external data memory Address Latch Enable signal. • RD – Port G, Bit the external data memory read control strobe. • WR – Port G, Bit the external data memory write control strobe. AT90CAN32/64/128 88 Port G Pins Alternate Functions Alternate Function TOSC1 (RTC Oscillator Timer/Counter2) ...
Page 89
... Overriding Signals for Alternate Functions in PG3:0 PG3/TOSC2 AS2 • EXCLK 0 AS2 • EXCLK AS2 0 – T/C2 OSC OUTPUT PORTA7 PORTA6 PORTA5 PORTA4 R/W R/W R/W R AT90CAN32/64/128 - PG4/TOSC1 AS2 0 AS2 AS2 EXCLK – T/C2 OSC INPUT PG2/ALE PG1/RD SRE SRE 0 0 SRE SRE 1 1 SRE SRE ALE RD 0 ...
Page 90
... Port C Data Register – PORTC Bit Read/Write Initial Value 9.4.8 Port C Data Direction Register – DDRC Bit Read/Write Initial Value 9.4.9 Port C Input Pins Address – PINC Bit Read/Write Initial Value AT90CAN32/64/128 DDA7 DDA6 DDA5 DDA4 R/W R/W R/W R/W 0 ...
Page 91
... PINE4 R/W R/W R/W R/W N/A N/A N/A N PORTF7 PORTF6 PORTF5 PORTF4 R/W R/W R/W R DDF7 DDF6 DDF5 DDF4 R/W R/W R/W R AT90CAN32/64/128 PORTD3 PORTD2 PORTD1 PORTD0 R/W R/W R/W R DDD3 DDD2 DDD1 DDD0 R/W R/W R/W R PIND3 PIND2 PIND1 PIND0 ...
Page 92
... Port G Data Register – PORTG Bit Read/Write Initial Value 9.4.20 Port G Data Direction Register – DDRG Bit Read/Write Initial Value 9.4.21 Port G Input Pins Address – PING Bit Read/Write Initial Value AT90CAN32/64/128 PINF7 PINF6 PINF5 PINF4 PINF3 R/W R/W R/W R/W ...
Page 93
... Characteristics (1)” on page 37. If the level is sampled twice by the Watchdog Oscillator clock but disappears before ISC31 ISC30 ISC21 ISC20 R/W R/W R/W R Table AT90CAN32/64/128 37. Low level interrupts and the ISC11 ISC10 ISC01 ISC00 R/W R/W R/W R 10-1. Edges on INT3..INT0 are registered asynchro- 365. The MCU “ ...
Page 94
... If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. Table 10-3. ISCn1 Note: AT90CAN32/64/128 94 Asynchronous External Interrupt Sense Control ISCn0 Description 0 The low level of INTn generates an interrupt request. 1 Any logical change on INTn generates an interrupt request 0 The falling edge of INTn generates asynchronously an interrupt request ...
Page 95
... Enable and Sleep Modes” on page 70 7679H–CAN–08/ INT7 INT6 INT5 INT4 INT3 R/W R/W R/W R INTF7 INTF6 INTF5 INTF4 INTF3 R/W R/W R/W R for more information. AT90CAN32/64/128 INT2 INT1 IINT0 EIMSK R/W R/W R/W R INTF2 INTF1 IINTF0 EIFR R/W R/W R/W R “Digital Input 95 ...
Page 96
... The latch is transparent in the high period of the internal system clock. clk I/O The edge detector generates one clk tive (CSn2 edge it detects. AT90CAN32/64/128 96 ). Alternatively, one of four taps from the prescaler can be used as a CLK_I/O /clk ). The T3/T1/T0 pin is sampled once every system clock cycle by the pin syn- ...
Page 97
... Since the edge detector uses ExtClk clk_I/O CK PSR310 0 CS00 CS10 CS01 CS11 CS02 CS12 TIMER/COUNTER0 CLOCK SOURCE clk T0 1. The synchronization logic on the input pins ( AT90CAN32/64/128 D Q Edge Detector 10-BIT T/C PRESCALER Clear 0 0 CS30 CS31 CS32 TIMER/COUNTER1 CLOCK SOURCE TIMER/COUNTER3 CLOCK SOURCE clk T1 T0/T1/T3) ...
Page 98
... When this bit is one, Timer/Counter3, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter3, Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect these three timers. AT90CAN32/64/128 ...
Page 99
... Configurations” on page “8-bit Timer/Counter Register Description” on page TCCRn count clear Control Logic direction BOTTOM TOP Timer/Counter TCNTn = 0 = 0xFF = OCRnx AT90CAN32/64/128 Figure 12-1. For the actual 5. CPU accessible I/O Registers, 109. TOVn (Int.Req.) Clock Select clk Tn Edge Tn Detector ( From Prescaler ) OCn (Int.Req.) ...
Page 100
... The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 12-2 shows a block diagram of the counter and its surroundings. Figure 12-2. Counter Unit Block Diagram AT90CAN32/64/128 100 for details. The compare match event will also set the Compare The counter reaches the BOTTOM when it becomes 0x00. ...
Page 101
... Signalize that TCNT0 has reached maximum value. Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 104. (See “Modes of Operation” on page AT90CAN32/64/128 in the following. T0 104.). 101 ...
Page 102
... TCNT0 when using the Output Compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0A value, the compare match will be missed, resulting in incorrect waveform AT90CAN32/64/128 102 shows a block diagram of the Output Compare unit. ...
Page 103
... The design of the Output Compare pin logic allows initialization of the OC0A state before the output is enabled. Note that some COM0A1:0 bit settings are reserved for certain modes of operation. 7679H–CAN–08/08 COMnx1 Waveform COMnx0 Generator FOCnx clk I/O See “8-bit Timer/Counter Register Description” on page 109. AT90CAN32/64/128 Figure 12 OCnx PORT D Q ...
Page 104
... The timing diagram for the CTC mode is shown in increases until a compare match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. AT90CAN32/64/128 104 Table 12-2 on page 110, and for phase correct PWM refer to (See “ ...
Page 105
... The diagram includes non-inverted and 7679H–CAN–08/08 TCNTn OCnx (Toggle) Period ------------------------------------------------- - ⋅ OCnx 2 N Figure 12-6. The TCNT0 value is in the timing diagram shown as a his- AT90CAN32/64/128 clk_I/O ⋅ OCRnx OCnx Interrupt Flag Set (COMnx1 OC0A 105 ...
Page 106
... OC0A to toggle its logical level on each compare match (COM0A1:0 = 1). The waveform generated will have a maximum frequency of f feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. AT90CAN32/64/128 106 TCNTn OCnx ...
Page 107
... OCR0A and TCNT0 when the counter increments, and setting (or clearing) the OC0A Register at compare match between OCR0A and TCNT0 when the counter 7679H–CAN–08/08 TCNTn OCnx OCnx Period 1 AT90CAN32/64/128 OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set (COMnx1 (COMnx1 ...
Page 108
... MAX value in all modes other than phase correct PWM mode. Figure 12-8. Timer/Counter Timing Diagram, no Prescaling Figure 12-9 Figure 12-9. Timer/Counter Timing Diagram, with Prescaler (f AT90CAN32/64/128 108 f OCnxPCPWM Figure 12-8 contains timing data for basic Timer/Counter operation. The figure ...
Page 109
... OCF0A and the clearing of TCNT0 in CTC mode. caler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC) OCRnx OCFnx FOC0A WGM00 COM0A1 COM0A0 W R/W R/W R AT90CAN32/64/128 OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP WGM01 CS02 CS01 CS00 TCCR0A R/W R/W R/W R /8) clk_I/O OCRnx + 2 BOTTOM + 1 109 ...
Page 110
... When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM01:0 bit setting. are set to a normal or CTC mode (non-PWM). Table 12-2. COM0A1 Table 12-3 mode. Table 12-3. COM0A1 AT90CAN32/64/128 110 104. Waveform Generation Mode Bit Description WGM01 WGM00 Timer/Counter (CTC0) (PWM0) Mode of Operation 0 0 Normal 0 1 PWM, Phase Correct 1 ...
Page 111
... I External clock source on T0 pin. Clock on falling edge External clock source on T0 pin. Clock on rising edge TCNT0[7:0] R/W R/W R/W R AT90CAN32/64/128 “Fast PWM Mode” on page 105 (1) “Phase Correct PWM Mode” TCNT0 R/W R/W R/W R 111 ...
Page 112
... Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Inter- rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at 0x00. AT90CAN32/64/128 112 ...
Page 113
... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the 7679H–CAN–08/08 “Pin Configurations” on page “16-bit Timer/Counter Register Description” on page AT90CAN32/64/128 Figure 13-1. For the actual 5. CPU accessible I/O Registers, 135. ...
Page 114
... Interrupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler external clock source on the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter AT90CAN32/64/128 114 Count ...
Page 115
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCR dependent of the mode of operation. AT90CAN32/64/128 T n See “Output Compare ...
Page 116
... Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCRnx 16-bit registers does not involve using the temporary register 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. AT90CAN32/64/128 116 7679H–CAN–08/08 ...
Page 117
... Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF sts TCNTnH,r17 sts TCNTnL,r16 ; Read TCNTn into r17:r16 lds r16,TCNTnL lds r17,TCNTnH ... (1) unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into TCNTn; ... 1. The example code assumes that the part specific header file is included. AT90CAN32/64/128 117 ...
Page 118
... Read TCNTn into TCNTn; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: The assembly code example returns the TCNTn value in the r17:r16 register pair. AT90CAN32/64/128 118 (1) r18,SREG r16,TCNTnL r17,TCNTnH SREG,r18 (1) 1. The example code assumes that the part specific header file is included. ...
Page 119
... Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNTn TCNTn = i; /* Restore global interrupt flag */ SREG = sreg; 1. The example code assumes that the part specific header file is included. “Timer/Counter3/1/0 Prescalers” on page AT90CAN32/64/128 96. 119 ...
Page 120
... There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OCnx. For more details about advanced counting sequences and waveform generation, see AT90CAN32/64/128 120 shows a block diagram of the counter and its surroundings. ...
Page 121
... ICRn (16-bit Register) WRITE ICP3 ACIC* ICP1 ACO* Analog Comparator The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 IC Unit– not Timer/Counter3. AT90CAN32/64/128 Figure 13-3. The elements of DATA BUS (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC3 ICES3 ...
Page 122
... In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the ICRn Register should be read as early in the inter- rupt handler routine as possible. Even though the Input Capture interrupt has relatively high AT90CAN32/64/128 122 116. ...
Page 123
... Waveform Generator. Figure 13-4 gram that are not directly a part of the Output Compare unit are gray shaded. 7679H–CAN–08/08 (See “Modes of Operation” on page shows a block diagram of the Output Compare unit. The elements of the block dia- AT90CAN32/64/128 126.) 123 ...
Page 124
... In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOCnx) bit. Forcing compare match will not set the OCFnx flag or reload/clear the timer, but the OCnx pin will be updated real compare AT90CAN32/64/128 124 TEMP (8-bit) OCRnxH Buf ...
Page 125
... PORT) that are affected by the COMnx1:0 bits are shown. When referring to the OCnx state, the reference is for the internal OCnx Register, not the OCnx pin system reset occur, the OCnx Register is reset to “0”. 7679H–CAN–08/08 AT90CAN32/64/128 Figure 13-5 shows a simplified 125 ...
Page 126
... The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Output mode (COMnx1:0) bits. The Compare Output mode bits do not affect the counting sequence, AT90CAN32/64/128 126 COMnx1 Waveform ...
Page 127
... OCRnA or ICRn, and then counter (TCNTn) is cleared. Figure 13-6. CTC Mode, Timing Diagram 7679H–CAN–08/08 “Timer/Counter Timing Diagrams” on page TCNTn OCnA (Toggle) Period 1 2 AT90CAN32/64/128 125.) 134. Figure 13-6. The counter value (TCNTn) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 ...
Page 128
... ICRn (WGMn3:0 = 14), or the value in OCRnA (WGMn3:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in AT90CAN32/64/128 128 = f /2 when OCRnA is set to zero (0x0000). The waveform frequency is ...
Page 129
... PWM frequency is actively changed (by changing the TOP value), using the OCRnA as TOP is clearly a better choice due to its double buffer feature. 7679H–CAN–08/08 TCNTn OCnx OCnx Period AT90CAN32/64/128 OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 ...
Page 130
... TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on shows phase correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn AT90CAN32/64/128 130 Table on page ...
Page 131
... OCnx value will only be visible on the port pin if the data direction for the port pin is set as 7679H–CAN–08/08 TCNTn OCnx OCnx Period 1 AT90CAN32/64/128 OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) ...
Page 132
... The diagram includes non- inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes repre- sent compare matches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a compare match occurs. AT90CAN32/64/128 132 f OCnxPCPWM 13-9) ...
Page 133
... TCNTn OCnx OCnx Period 1 2 shows the output generated is, in contrast to the phase correct mode, symmetri- f OCnxPFCPWM AT90CAN32/64/128 OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) (COMnx1 (COMnx1 ...
Page 134
... PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn flag at BOTTOM. AT90CAN32/64/128 134 Figure 13-10 shows a timing diagram for the setting of OCFnx. ...
Page 135
... TOP COM1A1 COM1A0 COM1B1 COM1B0 R/W R/W R/W R COM3A1 COM3A0 COM3B1 COM3B0 R/W R/W R/W R AT90CAN32/64/128 TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O TOP BOTTOM TOP TOP - 1 New OCRnx Value COM1C1 COM1C0 WGM11 WGM10 TCCR1A R/W R/W R/W R COM3C1 COM3C0 ...
Page 136
... When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is dependent of the WGMn3:0 bits setting. the WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM). Table 13-1. COMnA1/COMnB1/ COMnC1 Table 13-2 PWM mode. Table 13-2. COMnA1/COMnB1/ COMnC1 Note: AT90CAN32/64/128 136 Table 13-1 Compare Output Mode, non-PWM COMnA0/COMnB0/ COMnC0 ...
Page 137
... A special case occurs when OCnA/OCnB/OCnC equals TOP and COMnA1/COMnB1/COMnC1 is set. details. Table 13-4. Modes of operation supported by the Timer/Counter AT90CAN32/64/128 Description Normal port operation, OCnA/OCnB/OCnC disconnected. WGMn3=0: Normal port operation, OCnA/OCnB/OCnC disconnected. WGMn3=1: Toggle OCnA on Compare Match, OCnB/OCnC reserved. Clear OCnA/OCnB/OCnC on Compare Match when up-counting ...
Page 138
... Input Capture pin (ICPn) is filtered. The filter function requires four successive equal valued samples of the ICPn pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. • Bit 6 – ICESn: Input Capture Edge Select AT90CAN32/64/128 138 (1) WGMn0 ...
Page 139
... I clk /256 (From prescaler) I clk /1024 (From prescaler) I External clock source on Tn pin. Clock on falling edge External clock source on Tn pin. Clock on rising edge FOC1A FOC1B FOC1C – R/W R/W R AT90CAN32/64/128 – – – – TCCR1C Figure 139 ...
Page 140
... Registers” on page 116. Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a com- pare match between TCNTn and one of the OCRnx Registers. Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock for all compare units. AT90CAN32/64/128 140 ...
Page 141
... R/W R OCR3A[15:8] OCR3A[7:0] R/W R/W R/W R OCR3B[15:8] OCR3B[7:0] R/W R/W R/W R OCR3C[15:8] OCR3C[7:0] R/W R/W R/W R See “Accessing 16-bit Registers” on page 116. AT90CAN32/64/128 OCR1AH OCR1AL R/W R/W R/W R OCR1BH OCR1BL R/W R/W R/W R OCR1CH OCR1CL R/W R/W R/W R OCR3AH OCR3AL ...
Page 142
... This bit is reserved for future use. • Bit 3 – OCIEnC: Output Compare C Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding Interrupt Vector TIFRn, is set. AT90CAN32/64/128 142 ...
Page 143
... OCFnA flag, located in 60.) is executed when the TOVn flag, located in TIFRn, is set – – ICF1 – OCF1C R R R – – ICF3 – OCF3C R R R AT90CAN32/64/128 OCF1B OCF1A TOV1 TIFR1 R/W R/W R OCF3B OCF3A TOV3 TIFR3 R/W R/W R 143 ...
Page 144
... TOVn flag is set when the timer overflows. Refer to flag behavior when using another WGMn3:0 bit setting. TOVn is automatically cleared when the Timer/Countern Overflow Interrupt Vector is executed. Alternatively, TOVn can be cleared by writing a logic one to its bit location. AT90CAN32/64/128 144 Table 13-4 on page 138 for the TOVn ...
Page 145
... I/O pins, refer to Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the 7679H–CAN–08/08 AT90CAN32/64/128 Figure 1-2 on page 5 or Figure 1-3 on page “8-bit Timer/Counter Register Description” on page Figure 14-1 ...
Page 146
... The result of the compare can be used by the Waveform Generator to gener- ate a PWM or variable frequency output on the Output Compare pin (OC2A). Compare Unit” on page 148. (OCF2A) which can be used to generate an Output Compare interrupt request. AT90CAN32/64/128 146 TCCRnx count ...
Page 147
... Clear TCNT2 (set all bits to zero). Timer/Counter clock. T2 Signalizes that TCNT2 has reached maximum value. Signalizes that TCNT2 has reached minimum value (zero). AT90CAN32/64/128 . When the AS2 bit in the ASSR Register I/O 160. For details on clock sources and prescaler, see TOVn (Int ...
Page 148
... The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2A Compare AT90CAN32/64/128 148 ). clk can be generated from an external or internal clock source, ...
Page 149
... I/O pins in the figure are shown in bold. Only the parts of the general I/O port control regis- ters (DDR and PORT) that are affected by the COM2A1:0 bits are shown. When referring to the OC2A state, the reference is for the internal OC2A Register, not the OC2A pin. 7679H–CAN–08/08 AT90CAN32/64/128 Figure 14-5 shows a sim- 149 ...
Page 150
... Waveform Generation mode bits do. The COM2A1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM2A1:0 bits control whether the output should be set, cleared, or toggled at a compare match AT90CAN32/64/128 150 COMnx1 Waveform ...
Page 151
... Timing Diagrams” on page TCNTn OCnx (Toggle) Period 1 2 AT90CAN32/64/128 155. Figure 14-6. The counter value (TCNT2) OCnx Interrupt Flag Set (COMnx1 151 ...
Page 152
... PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2A and TCNT2. Figure 14-7. Fast PWM Mode, Timing Diagram AT90CAN32/64/128 152 f = OCnx Figure 14-7 ...
Page 153
... The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2A and TCNT2. 7679H–CAN–08/08 AT90CAN32/64/128 Table 14-3 on page f clk_I/O ...
Page 154
... Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match. • OCR2A changes its value from MAX, like in value is MAX the OCn pin value is the same as the result of a down-counting compare AT90CAN32/64/128 154 TCNTn OCnx ...
Page 155
... MAX - 1 TOVn shows the same timing data, but with the prescaler enabled. clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn shows the setting of OCF2A in all modes except CTC mode. AT90CAN32/64/128 should be replaced by I/O MAX BOTTOM /8) clk_I/O MAX BOTTOM ) T2 BOTTOM + 1 BOTTOM + 1 155 ...
Page 156
... Figure 14-11. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f AT90CAN32/64/128 156 clk I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx clk_I/O OCRnx OCRnx + 1 OCRnx Value 7679H–CAN–08/08 /8) OCRnx + 2 ...
Page 157
... OCF2A and the clearing of TCNT2 in CTC mode. caler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC) OCRnx OCFnx FOC2A WGM20 COM2A1 COM2A0 W R/W R/W R AT90CAN32/64/128 TOP BOTTOM TOP WGM21 CS22 CS21 CS20 TCCR2A R/W R/W R/W R BOTTOM + 1 157 ...
Page 158
... WGM21:0 bit setting. are set to a normal or CTC mode (non-PWM). Table 14-2. COM2A1 Table 14-3 mode. Table 14-3. COM2A1 Note: AT90CAN32/64/128 158 150. Waveform Generation Mode Bit Description WGM21 WGM20 Timer/Counter (CTC2) (PWM2) Mode of Operation 0 0 Normal 0 1 PWM, Phase Correct 1 ...
Page 159
... R/W R/W R/W R OCR2A[7:0] R/W R/W R/W R AT90CAN32/64/128 (1) “Phase Correct PWM Mode” on Description No clock source (Timer/Counter stopped). clk /(No prescaling) T2S clk /8 (From prescaler) T2S clk /32 (From prescaler) T2S clk /64 (From prescaler) T2S clk /128 (From prescaler) T2S clk /256 (From prescaler) ...
Page 160
... The mechanisms for reading TCNT2, OCR2A, and TCCR2A are different. When reading TCNT2, the actual timer value is read. When reading OCR2A or TCCR2A, the value in the tem- porary storage register is read. AT90CAN32/64/128 160 7 6 ...
Page 161
... Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. 7679H–CAN–08/08 Enable interrupts, if needed. AT90CAN32/64/128 161 ...
Page 162
... Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register – TIFR2. 14.10.4 Timer/Counter2 Interrupt Flag Register – TIFR2 Bit Read/Write Initial Value AT90CAN32/64/128 162 ) again becomes active, TCNT2 will read as the previous value (before entering I – ...
Page 163
... AS2 EXCLK clk Enable TOSC2 I kHz 0 Oscillator 1 TOSC1 1 EXCLK AS2 PSR2 CS20 CS21 CS22 . By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously IO AT90CAN32/64/128 clk T2S 10-BIT T/C PRESCALER Clear 0 TIMER/COUNTER2 CLOCK SOURCE clk T2 . clk is by default connected to the main T2S T2S 163 ...
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... If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the chronization Mode” on page 98 AT90CAN32/64/128 164 32.768 KHz ...
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... Timer/Counter units and the port B pin 7 output driver circuit. 7679H–CAN–08/08 “16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)” and “8-bit Timer/Counter0 with PWM” on page Timer/Counter 1 OC1C Timer/Counter 0 OC0A (Figure 15-1). AT90CAN32/64/128 99. Pin OC0A / OC1C / PB7 Figure 15-2. The schematic 165 ...
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... Compare Output mode (COMnx1:0 = 1). Figure 15-3. Output Compare Modulator, Timing Diagram In this example, Timer/Counter0 provides the carrier, while the modulating signal is generated by the Output Compare unit C of the Timer/Counter1. AT90CAN32/64/128 166 Modulator DATABUS illustrates the modulator in action. In this example the Timer/Counter1 is set to oper- ...
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... The reason for the reduction is illustrated in 15-3 at the second and third period of the PB7 output when PORTB7 equals zero. The period 2 high time is one cycle longer than the period 3 high time, but the result on the PB7 output is equal in both periods. 7679H–CAN–08/08 AT90CAN32/64/128 Figure 167 ...
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... Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90CAN32/64/128 and peripheral devices or between several AVR devices. The AT90CAN32/64/128 SPI includes the following features: 16.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • ...
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... In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high period should be: – Low period: Longer than 2 CPU clock cycles, – High period: Longer than 2 CPU clock cycles. 7679H–CAN–08/08 AT90CAN32/64/128 Figure 16-2. The sys- SHIFT ENABLE ...
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... When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 16-1. Pin MOSI MISO SCK SS Note: AT90CAN32/64/128 170 Table 16-1. For more details on automatic port overrides, refer to 71. (1) SPI Pin Overrides Direction, Master SPI User Defined Input ...
Page 171
... DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))); 1. The example code assumes that the part specific header file is included. AT90CAN32/64/128 171 ...
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... When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which AT90CAN32/64/128 172 (1) r17,(1< ...
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... This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero configured as an input and is driven low while MSTR is set, MSTR will be cleared, 7679H–CAN–08/ SPIE SPE DORD MSTR CPOL R/W R/W R/W R/W R AT90CAN32/64/128 CPHA SPR1 SPR0 SPCR R/W R/W R 173 ...
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... These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the clk the following table: Table 16-4. SPI2X AT90CAN32/64/128 174 Figure 16-3 and Figure 16-4 CPOL Functionality ...
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... SPI Data Register. • Bit 5..1 – Res: Reserved Bits These bits are reserved bits in the AT90CAN32/64/128 and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods ...
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... Table 16-2 Table 16-5. CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 Figure 16-3. SPI Transfer Format with CPHA = 0 Figure 16-4. SPI Transfer Format with CPHA = 1 AT90CAN32/64/128 176 and Table 16-3, as done below: CPOL Functionality Leading Edge Sample (Rising) Setup (Rising) ...
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... USART0 I/O data value and so on. 17.3 Dual USART The AT90CAN32/64/128 has two USART’s, USART0 and USART1. The functionality for both USART’s is described below. USART0 and USART1 have different I/O registers as shown in “Register Summary” on page A simplified block diagram of the USARTn Transmitter is shown in I/O Registers and I/O pins are shown in bold. 7679H– ...
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... The recovery units are used for asynchronous data reception. In addition to the recovery units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors. AT90CAN32/64/128 178 (1) UBRRn[H:L] ...
Page 179
... Transmitter clock (Internal Signal). Receiver base clock (Internal Signal). Input from XCK pin (internal Signal). Used for synchronous slave operation. Clock output to XCK pin (Internal Signal). Used for synchronous master operation. clk System I/O Clock frequency. io AT90CAN32/64/128 Edge Detector UCPOLn Figure 17-2 ...
Page 180
... Transmitter and Receiver. This process intro- duces a two CPU clock period delay and therefore the maximum external XCKn clock frequency is limited by the following equation: AT90CAN32/64/128 180 contains equations for calculating the baud rate (in bits per second) and for calculat- ...
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... It is therefore recommended io UCPOLn = 1 XCKn RxDn / TxDn UCPOLn = 0 XCKn RxDn / TxDn Figure 17-3 shows, when UCPOLn is zero the data will be changed illustrates the possible combinations of the frame formats. Bits inside brackets are AT90CAN32/64/128 Sample Sample 181 ...
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... Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. The TXCn flag can be used to check that the Transmitter has completed all transfers, and the RXCn flag can be used to AT90CAN32/64/128 182 FRAME ...
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... UBRR0L = (unsigned char) baud; /* Set frame format: 8data, no parity & 2 stop bits */ UCSR0C = (0<<UMSEL0) | (0<<UPM0) | (1<<USBS0) | (3<<UCSZ0); /* Enable receiver and transmitter */ UCSR0B = (1<<RXEN0) | (1<<TXEN0); 1. The example code assumes that the part specific header file is included. AT90CAN32/64/128 183 ...
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... Note: The function simply waits for the transmit buffer to be empty by checking the UDRE0 flag, before loading it with new data to be transmitted. If the Data Register Empty interrupt is utilized, the interrupt routine writes the data into the buffer. AT90CAN32/64/128 184 (1) r17, UCSR0A ...
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... These transmit functions are written to be general functions. They can be optimized if the con- tents of the UCSR0B is static. For example, only the TXB80 bit of the UCSRB0 Register is used after initialization. 2. The example code assumes that the part specific header file is included. AT90CAN32/64/128 185 ...
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... When the first stop bit is received, i.e., a complete serial frame is present in the Receive Shift Register, the contents of the Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDRn I/O location. AT90CAN32/64/128 186 7679H–CAN–08/08 ...
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... Get and return received data from buffer lds r16, UDR0 ret (1) /* Wait for data to be received */ while ( ! (UCSR0A & (1<<RXC0))); /* Get and return received data from buffer */ return UDR0; 1. The example code assumes that the part specific header file is included. AT90CAN32/64/128 187 ...
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... Note: The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. AT90CAN32/64/128 188 (1) r18, UCSR0A ...
Page 189
... The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPEn) flag can then be read by software to check if the frame had a Parity Error. 7679H–CAN–08/08 “Parity Bit Calculation” on page 182 AT90CAN32/64/128 and “Parity Checker” on page 189. 189 ...
Page 190
... The clock recovery logic synchronizes internal clock to the incoming serial frames. illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The hor- AT90CAN32/64/128 190 (1) ...
Page 191
... Including the first stop bit. Note that the Receiver only uses the first stop bit of a frame. 7679H–CAN–08/08 RxDn IDLE Sample (U2Xn = Sample (U2Xn = RxDn Sample Sample AT90CAN32/64/128 START Figure 17-6 shows the sampling of the data bits and BIT ...
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... Table 17-2 that Normal Speed mode has higher toleration of baud rate variations. AT90CAN32/64/128 192 shows the sampling of the stop bit and the earliest possible beginning of the start bit RxDn 1 ...
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... AT90CAN32/64/128 Recommended Max Max Total Error (%) Receiver Error (%) +6.67/-6.8 ± 3.0 +5.79/-5.88 ± 2.5 +5.11/-5.19 ± 2.0 +4.58/-4.54 ± 2.0 +4.14/-4.19 ± 1.5 +3.78/-3.83 ± 1.5 ...
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... Transmitter and Receiver use the same character size set- ting 8-bit character frames are used, the Transmitter must be set to use two stop bit (USBSn = 1) since the first stop bit is used for indicating the frame type. AT90CAN32/64/128 194 7679H–CAN–08/08 ...
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... RXB1[7:0] TXB1[7:0] R/W R/W R/W R/W R RXC0 TXC0 UDRE0 FE0 DOR0 R R RXC1 TXC1 UDRE1 FE1 DOR1 R R AT90CAN32/64/128 UDR0 (Read) UDR0 (Write) R/W R/W R UDR1 (Read) UDR1 (Write) R/W R/W R UPE0 U2X0 MPCM0 UCSR0A R R R/W R UPE1 U2X1 MPCM1 UCSR1A ...
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... USARnT Receiver that do not contain address information will be ignored. The Transmitter is unaffected by the MPCMn setting. For more detailed information see 17.11.5 USART0 Control and Status Register B – UCSR0B Bit Read/Write Initial Value AT90CAN32/64/128 196 “Multi-processor Communication Mode” on page RXCIE0 ...
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... USART0 Control and Status Register C – UCSR0C Bit Read/Write Initial Value 7679H–CAN–08/ RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 R/W R/W R/W R – UMSEL0 UPM01 UPM00 USBS0 R R/W R/W R AT90CAN32/64/128 UCSZ12 RXB81 TXB81 UCSR1B R/W R UCSZ01 UCSZ00 UCPOL0 UCSR0C R/W R/W R/W R 197 ...
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... If a mismatch is detected, the UPEn Flag in UCSRnA will be set. Table 17-5. UPMn1 • Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 17-6. AT90CAN32/64/128 198 – UMSEL1 ...
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... R/W R – – – – UBRR1[7: R/W R/W R/W R AT90CAN32/64/128 UCSZn0 Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 Reserved 0 Reserved 1 9-bit Received Data Sampled (Input on RxDn Pin) Falling XCK Edge Rising XCK Edge UBRR0[11:8] UBRR0H R/W R/W R/W R/W R/W R/W ...
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... Max. 62.5 Kbps 125 Kbps Note: 1. UBRRn = 0, Error = 0.0% AT90CAN32/64/128 200 Table 17-12. UBRRn values which yield an actual baud rate differing less than 0.5% “Asynchronous Operational Range” on page Error[%] = f = 1.8432 MHz clk io U2Xn = 0 U2Xn = 1 ...