PIC18F2480-E/SO Microchip Technology, PIC18F2480-E/SO Datasheet - Page 334
![IC PIC MCU FLASH 8KX16 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18F2480-E/SO
Manufacturer Part Number
PIC18F2480-E/SO
Description
IC PIC MCU FLASH 8KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F4480-IPT.pdf
(490 pages)
4.PIC18F4480-IPT.pdf
(8 pages)
5.PIC18F4480-IPT.pdf
(6 pages)
6.PIC18F4480-IPT.pdf
(6 pages)
7.PIC18LF2480-ISP.pdf
(14 pages)
8.PIC18F2580-ESO.pdf
(483 pages)
Specifications of PIC18F2480-E/SO
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI/I2C/MSSP/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163011, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2480-E/SO
Manufacturer:
Microchip Technology
Quantity:
135
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F4480-IPT PDF datasheet #3
- PIC18F4480-IPT PDF datasheet #4
- PIC18F4480-IPT PDF datasheet #5
- PIC18F4480-IPT PDF datasheet #6
- PIC18LF2480-ISP PDF datasheet #7
- PIC18F2580-ESO PDF datasheet #8
- Current page: 334 of 483
- Download datasheet (9Mb)
PIC18F2480/2580/4480/4580
23.9
All nodes on a given CAN bus must have the same
nominal bit rate. The CAN protocol uses Non-Return-
to-Zero (NRZ) coding which does not encode a clock
within the data stream. Therefore, the receive clock
must be recovered by the receiving nodes and
synchronized to the transmitter’s clock.
As oscillators and transmission time may vary from
node to node, the receiver must have some type of
Phase Lock Loop (PLL) synchronized to data transmis-
sion edges to synchronize and maintain the receiver
clock. Since the data is NRZ coded, it is necessary to
include bit stuffing to ensure that an edge occurs at
least every six bit times to maintain the Digital Phase
Lock Loop (DPLL) synchronization.
The bit timing of the PIC18F2480/2580/4480/4580 is
implemented using a DPLL that is configured to syn-
chronize to the incoming data and provides the nominal
timing for the transmitted data. The DPLL breaks each
bit time into multiple segments made up of minimal
periods of time called the Time Quanta (T
Bus timing functions executed within the bit time frame,
such as synchronization to the local oscillator, network
transmission delay compensation and sample point
positioning, are defined by the programmable bit timing
logic of the DPLL.
All devices on the CAN bus must use the same bit rate.
However, all devices are not required to have the same
master oscillator clock frequency. For the different clock
frequencies of the individual devices, the bit rate has to
be adjusted by appropriately setting the baud rate
prescaler and number of time quanta in each segment.
The Nominal Bit Rate is the number of bits transmitted
per second, assuming an ideal transmitter with an ideal
oscillator, in the absence of resynchronization. The
nominal bit rate is defined to be a maximum of 1 Mb/s.
The Nominal Bit Time is defined as:
EQUATION 23-1:
FIGURE 23-4:
DS39637C-page 332
Input
Signal
Bit
Time
Intervals
T
Baud Rate Setting
Q
T
BIT
= 1/Nominal Bit Rate
Segment
BIT TIME PARTITIONING
Sync
Sync
Propagation
Segment
Q
).
Preliminary
Segment 1
Phase
Nominal Bit Time
The Nominal Bit Time can be thought of as being
divided into separate, non-overlapping time segments.
These segments (Figure 23-4) include:
• Synchronization Segment (Sync_Seg)
• Propagation Time Segment (Prop_Seg)
• Phase Buffer Segment 1 (Phase_Seg1)
• Phase Buffer Segment 2 (Phase_Seg2)
The time segments (and thus the Nominal Bit Time) are
in turn made up of integer units of time called Time
Quanta or T
Nominal Bit Time is programmable from a minimum of
8 T
minimum Nominal Bit Time is 1 μs, corresponding to a
maximum 1 Mb/s rate. The actual duration is given by
the following relationship.
EQUATION 23-2:
The Time Quantum is a fixed unit derived from the
oscillator period. It is also defined by the programmable
baud rate prescaler, with integer values from 1 to 64, in
addition to a fixed divide-by-two for clock generation.
Mathematically, this is:
EQUATION 23-3:
where F
corresponding oscillator period and BRP is an integer
(0 through 63) represented by the binary values of
BRGCON1<5:0>. The equation above refers to the
effective clock frequency used by the microcontroller. If,
for example, a 10 MHz crystal in HS mode is used, then
the F
10 MHz crystal is used in HS-PLL mode, then the
effective frequency is F
Q
Nominal Bit Time = T
OSC
to a maximum of 25 T
Sample Point
OSC
T
= 10 MHz and T
T
Q
Q
(μs) = (2 * (BRP+1))/F
Q
(μs) = (2 * (BRP+1)) * T
Phase_Seg1 + Phase_Seg2)
is the clock frequency, T
(see Figure 23-4). By definition, the
OSC
© 2007 Microchip Technology Inc.
Q
Segment 2
* (Sync_Seg + Prop_Seg +
or
= 40 MHz and T
Phase
OSC
Q
. Also by definition, the
= 100 ns. If the same
OSC
OSC
(MHz)
(μs)
OSC
OSC
= 25 ns.
is the
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