ATMEGA32U4-AU Atmel, ATMEGA32U4-AU Datasheet - Page 430

• Manufacturer Part Number: ATMEGA32U4-AU
• Description: MCU AVR 32K FLASH 16MHZ 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32U4-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2.5 KB
• Interface Type: SPI/TWI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 2.5KB
• # I/os (max): 26
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• Controller Family/series: AVR MEGA
• No. Of I/o's: 26
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2.5KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA32U4-16AU; ATMEGA32U4-16AU

vi
ATmega16/32U4
25 JTAG Interface and On-chip Debug System ..................................... 314
26 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 320
27 Boot Loader Support – Read-While-Write Self-Programming ......... 330
28 Memory Programming ......................................................................... 346
24.8ADC Conversion Result ......................................................................................305
24.9ADC Register Description ...................................................................................307
25.1Overview .............................................................................................................314
25.2Test Access Port – TAP ......................................................................................314
25.3TAP Controller .....................................................................................................316
25.4Using the Boundary-scan Chain ..........................................................................317
25.5Using the On-chip Debug System .......................................................................317
25.6On-chip Debug Specific JTAG Instructions .........................................................318
25.7On-chip Debug Related Register in I/O Memory .................................................319
25.8Using the JTAG Programming Capabilities .........................................................319
25.9Bibliography .........................................................................................................319
26.1Features ..............................................................................................................320
26.2System Overview ................................................................................................320
26.3Data Registers .....................................................................................................320
26.4Boundary-scan Specific JTAG Instructions .........................................................322
26.5Boundary-scan Related Register in I/O Memory .................................................323
26.6Boundary-scan Chain ..........................................................................................324
26.7ATmega16U4/ATmega32U4 Boundary-scan Order ............................................327
26.8Boundary-scan Description Language Files ........................................................329
27.1Boot Loader Features ..........................................................................................330
27.2Application and Boot Loader Flash Sections .......................................................330
27.3Read-While-Write and No Read-While-Write Flash Sections ..............................330
27.4Boot Loader Lock Bits .........................................................................................333
27.5Entering the Boot Loader Program ......................................................................334
27.6Addressing the Flash During Self-Programming .................................................337
27.7Self-Programming the Flash ................................................................................338
28.1Program And Data Memory Lock Bits .................................................................346
28.2Fuse Bits .............................................................................................................347
28.3Signature Bytes ...................................................................................................349
28.4Calibration Byte ...................................................................................................349
28.5Parallel Programming Parameters, Pin Mapping, and Commands .....................349
7766F–AVR–11/10