DSPIC30F2020-30I/SP Microchip Technology, DSPIC30F2020-30I/SP Datasheet - Page 106

• Manufacturer Part Number: DSPIC30F2020-30I/SP
• Description: IC DSPIC MCU/DSP 12K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2020-30I/SP

• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC30F1010/202X
FIGURE 11-1:
11.7
The output compare channels have the ability to gener-
ate an interrupt on a compare match, for whichever
Match mode has been selected.
For all modes except the PWM mode, when a compare
event occurs, the respective interrupt flag (OCxIF) is
asserted and an interrupt will be generated, if enabled.
The OCxIF bit is located in the corresponding IFS
STATUS register, and must be cleared in software. The
interrupt is enabled via the respective compare inter-
rupt enable (OCxIE) bit, located in the corresponding
IEC Control register.
For the PWM mode, when an event occurs, the respec-
tive timer interrupt flag (T2IF or T3IF) is asserted and
an interrupt will be generated, if enabled. The IF bit is
located in the IFS0 STATUS register, and must be
cleared in software. The interrupt is enabled via the
respective timer interrupt enable bit (T2IE or T3IE),
located in the IEC0 Control register. The output com-
pare interrupt flag is never set during the PWM mode of
operation.
DS70178C-page 104
Output Compare Interrupts
OCxR = OCxRS
TMR3 = PR3
(Interrupt Flag)
T3IF = 1
PWM OUTPUT TIMING
Duty Cycle
TMR3 = Duty Cycle (OCxR)
Period
Preliminary
OCxR = OCxRS
TMR3 = PR3
(Interrupt Flag)
T3IF = 1
TMR3 = Duty Cycle (OCxR)
© 2006 Microchip Technology Inc.