PIC18F4580-I/P Microchip Technology, PIC18F4580-I/P Datasheet - Page 42
![IC PIC MCU FLASH 16KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F4580-I/P
Manufacturer Part Number
PIC18F4580-I/P
Description
IC PIC MCU FLASH 16KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F4480-IPT.pdf
(490 pages)
4.PIC18F4480-IPT.pdf
(8 pages)
5.PIC18F4480-IPT.pdf
(6 pages)
6.PIC18F4480-IPT.pdf
(6 pages)
7.PIC18F2580-ESO.pdf
(483 pages)
Specifications of PIC18F4580-I/P
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
SPI/I2C/USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
35
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit
Package
40PDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4580-I/P
Manufacturer:
RENESAS
Quantity:
5 600
Part Number:
PIC18F4580-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
PIC18F4580-I/PT
Manufacturer:
MICROCHIP
Quantity:
201
Company:
Part Number:
PIC18F4580-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F4580-I/PT
Manufacturer:
MICROCHI
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F4480-IPT PDF datasheet #3
- PIC18F4480-IPT PDF datasheet #4
- PIC18F4480-IPT PDF datasheet #5
- PIC18F4480-IPT PDF datasheet #6
- PIC18F2580-ESO PDF datasheet #7
- Current page: 42 of 483
- Download datasheet (9Mb)
PIC18F2480/2580/4480/4580
3.5.4
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode where the primary clock source
• the primary clock source is not any of the LP, XT,
TABLE 3-2:
DS39637C-page 40
Note 1:
is not stopped; and
HS or HSPLL modes.
Primary Device Clock
T1OSC or INTRC
2:
3:
4:
5:
(PRI_IDLE mode)
Before Wake-up
Clock Source
(Sleep mode)
INTOSC
In this instance, refers specifically to the 31 kHz INTRC clock source.
T
with any other required delays (see Section 3.4 “Idle Modes”).
Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
T
also designated as T
Execution continues during T
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
CSD
OST
None
(parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently
is the Oscillator Start-up Timer (parameter 32). t
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
(3)
(1)
PLL
.
IOBST
After Wake-up
Clock Source
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
LP, XT, HS
INTOSC
INTRC
INTRC
INTRC
INTRC
EC, RC
EC, RC
EC, RC
EC, RC
HSPLL
HSPLL
HSPLL
HSPLL
(parameter 39), the INTOSC stabilization period.
Preliminary
(1)
(1)
(1)
(1)
(3)
(3)
(3)
(3)
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes). However, a fixed delay of interval,
T
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
CSD
rc
is the PLL Lock-out Timer (parameter F12); it is
, following the wake event is still required when
T
T
T
Exit Delay
OST
OST
OST
T
T
T
T
T
T
T
T
T
IOBST
IOBST (5)
None
CSD
CSD (2)
CSD (2)
CSD (2)
OST (4)
OST (5)
OST
+ t
+ t
+ t
(2)
(4)
rc
(5)
rc
rc
(4)
(4)
(4)
© 2007 Microchip Technology Inc.
Clock Ready Status
bit (OSCCON)
OSTS
OSTS
OSTS
OSTS
IOFS
IOFS
IOFS
IOFS
—
—
—
—
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