PIC18F2685-E/SP Microchip Technology, PIC18F2685-E/SP Datasheet - Page 37
![IC PIC MCU FLASH 48KX16 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F2685-E/SP
Manufacturer Part Number
PIC18F2685-E/SP
Description
IC PIC MCU FLASH 48KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PCM18XT0.pdf
(484 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2682-ISP.pdf
(6 pages)
4.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18F2685-E/SP
Core Size
8-Bit
Program Memory Size
96KB (48K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
28
Eeprom Memory Size
1024Byte
Ram Memory Size
3328Byte
Cpu Speed
40MHz
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
Details
- PCM18XT0 PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2682-ISP PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- Current page: 37 of 484
- Download datasheet (9Mb)
FIGURE 3-1:
FIGURE 3-2:
3.2.3
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer; the primary clock is shut down.
When using the INTRC source, this mode provides the
best power conservation of all the Run modes, while
still executing code. It works well for user applications
which are not highly timing sensitive or do not require
high-speed clocks at all times.
If the primary clock source is the internal oscillator
block (either INTRC or INTOSC), there are no distin-
guishable
RC_RUN modes during execution. However, a clock
switch delay will occur during entry to and exit from
RC_RUN mode. Therefore, if the primary clock source
is the internal oscillator block, the use of RC_RUN
mode is not recommended.
This mode is entered by setting SCS1 to ‘1’. Although
it is ignored, it is recommended that SCS0 also be
cleared; this is to maintain software compatibility with
future devices. When the clock source is switched to
© 2009 Microchip Technology Inc.
T1OSI
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
RC_RUN MODE
Note 1: T
differences
CPU Clock
PLL Clock
Peripheral
Program
Counter
Output
T1OSI
OSC1
Clock
Q1
SCS1:SCS0 bits Changed
OST
Q2
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
PC
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
= 1024 T
Q3
between
Q4
OSC
Q1
; T
Q1
PLL
1
T
OST
PRI_RUN
= 2 ms (approx). These intervals are not shown to scale.
(1)
PC
2
Q2
Clock Transition
PIC18F2682/2685/4682/4685
3
T
PLL (1)
OSTS bit Set
Q3
and
Q4
PC + 2
n-1
the INTOSC multiplexer (see Figure 3-3), the primary
oscillator is shut down and the OSTS bit is cleared. The
IRCF bits may be modified at any time to immediately
change the clock speed.
If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output is not enabled and the IOFS bit will
remain clear; there will be no indication of the current
clock source. The INTRC source is providing the
device clocks.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output) or if INTSRC is set, the
IOFS bit becomes set after the INTOSC output
becomes stable. Clocks to the device continue while
the INTOSC source stabilizes after an interval of
T
n
Q1
1
IOBST
Note:
Transition
2
Clock
.
n-1 n
Q2
Caution should be used when modifying a
single IRCF bit. If V
possible to select a higher clock speed
than is supported by the low V
Improper device operation may result if
the V
PC + 2
Q3
DD
/F
Q2
OSC
Q4
Q3 Q4
specifications are violated.
Q1
Q1
DD
PC + 4
Q2
PC + 4
is less than 3V, it is
Q2
DS39761C-page 37
Q3
Q3
DD
.
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