PIC18F6620-E/PT Microchip Technology, PIC18F6620-E/PT Datasheet - Page 16
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PIC18F6620-E/PT
Manufacturer Part Number
PIC18F6620-E/PT
Description
IC PIC MCU FLASH 32KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F8520T-IPT.pdf
(380 pages)
3.PIC18F8520T-IPT.pdf
(40 pages)
4.PIC18F6620-IPT.pdf
(14 pages)
5.PIC18F6620-IPT.pdf
(12 pages)
Specifications of PIC18F6620-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.75K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3840 B
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
52
Number Of Timers
2 x 8 bit
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F6620-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18FXX20
3.3
Data EEPROM is accessed one byte at a time via an
Address Pointer (register pair EEADR:EEADRH) and a
data latch (EEDATA). Data EEPROM is written by
loading EEADR:EEADRH with the desired memory
location, EEDATA with the data to be written, and
initiating a memory write by appropriately configuring
the EECON1 and EECON2 registers. A byte write
automatically erases the location and writes the new
data (erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, both the EEPGD and CFGS bits must
be cleared (EECON1<7:6> = 00). The WREN bit must
be set (EECON1<2> = 1) to enable writes of any sort,
and this must be done prior to initiating a write
sequence. The write sequence is initiated by setting the
WR bit (EECON1<1> = 1). It is strongly recommended
that the WREN bit be set only when absolutely
necessary.
To help prevent inadvertent writes when using the
EECON1 register, EECON2 is used to “enable” the WR
bit. This register must be sequentially loaded with 55h
and then AAh, immediately prior to asserting the WR bit
in order for the write to occur.
The write begins on the falling edge of the 4th SCLK
after the WR bit is set. It ends when the WR bit is
cleared by hardware.
After the programming sequence terminates, SCLK
must still be held low for the time specified by
parameter P10 to allow high voltage discharge of the
memory array.
FIGURE 3-9:
DS39583C-page 16
SCLK
SDATA
Poll WR bit
Data EEPROM Programming
4-bit Command
1
0
2
0
3
0
SDATA
SCLK
4
0
DATA EEPROM WRITE TIMING
P5
BSF EECON1, WR
1
4-bit Command
1
0
2
2
0
15 16
3
0
4
0
P5A
P5
MOVF EECON1, W, 0
1
2
SDATA = Input
SDATA = Input
15 16
P5A
4-bit Command
1
0
Poll WR bit, Repeat Until Clear
FIGURE 3-8:
2
0
3
0
(see below)
4
0
P5
MOVWF TABLAT
1
No
2
Unlock Sequence
15 16
55h - EECON2
AAh - EECON2
PROGRAM DATA FLOW
Enable Write
Set Address
Start Write
Sequence
2010 Microchip Technology Inc.
Set Data
WR bit
Clear ?
Done
Start
Done
P5A
?
Yes
Yes
(see Figure 4-6)
SDATA = Output
Shift Out Data
No
P10
16-bit Data
Payload
1
n
2
n