PIC18F2685-I/SO Microchip Technology, PIC18F2685-I/SO Datasheet - Page 360
![IC PIC MCU FLASH 48KX16 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18F2685-I/SO
Manufacturer Part Number
PIC18F2685-I/SO
Description
IC PIC MCU FLASH 48KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PCM18XT0.pdf
(484 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2682-ISP.pdf
(6 pages)
4.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18F2685-I/SO
Program Memory Type
FLASH
Program Memory Size
96KB (48K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PCM18XT0 PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2682-ISP PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- Current page: 360 of 484
- Download datasheet (9Mb)
PIC18F2682/2685/4682/4685
24.5
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other PIC
devices.
The user program memory is divided into five blocks.
One of these is a boot block of 2 Kbytes. The remainder
of the memory is divided into four blocks on binary
boundaries.
FIGURE 24-5:
DS39761C-page 360
Program Verification and
Code Protection
(PIC18F2682/4682)
Unimplemented
Unimplemented
80 Kbytes
Boot Block
Read ‘0’s
Read ‘0’s
Block 0
Block 1
Block 2
Block 3
Block 4
MEMORY SIZE/DEVICE
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2682/2685/4682/4685
(PIC18F2685/4685)
Unimplemented
96 Kbytes
Boot Block
Read ‘0’s
Block 0
Block 1
Block 2
Block 3
Block 4
Block 5
000000h
0007FFh
000800h
003FFFh
004000h
007FFFh
008000h
00BFFFh
00C000h
00FFFFh
010000h
013FFFh
014000h
017FFFh
018000h
1FFFFFh
Address
Range
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 24-5 shows the program memory organization
for 80- and 96-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 24-3.
(Unimplemented Memory Space)
Block Code Protection
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
CP4, WRT4, EBTR4
CP5, WRT5, EBTR5
Controlled By:
© 2009 Microchip Technology Inc.
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