Z8F012ASB020EG Zilog, Z8F012ASB020EG Datasheet - Page 61

• Manufacturer Part Number: Z8F012ASB020EG
• Description: IC ENCORE XP MCU FLASH 1K 8SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F012ASB020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 16 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: Z8F012Ax
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8F04A08100KITG, Z8F04A28100KITG, ZENETSC0100ZACG, ZENETSC0100ZACG, ZUSBOPTSC01ZACG, ZUSBSC00100ZAC, ZUSBSC00100ZACG
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4038; Z8F012ASB020EG

Table 24. Port A–D Pull-Up Enable Sub-Registers (PxPUE)
Table 25. Port A–D Alternate Function Set 1 Sub-Registers (PxAFS1)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS022825-0908
Note:
PAFS17
PPUE7
R/W
R/W
If 06H in Port A
If 07H in Port A–D Address Register, accessible through the Port A–D Control Register
7
7
0
during STOP mode do not initiate Stop Mode Recovery.
1 = The Port pin is configured as a Stop Mode Recovery source. Any logic transition on
this pin during STOP mode initiates Stop Mode Recovery.
Port A–D Pull-up Enable Sub-Registers
The Port A–D Pull-up Enable sub-register
Control register by writing
Port A–D Pull-up Enable sub-registers enables a weak internal resistive pull-up on the
specified Port pins.
PPUE[7:0]—Port Pull-up Enabled
0 = The weak pull-up on the Port pin is disabled.
1 = The weak pull-up on the Port pin is enabled.
Port A–D Alternate Function Set 1 Sub-Registers
The Port A–D Alternate Function Set1 sub-register
A–D Control register by writing
Function Set 1 sub-registers selects the alternate function available at a port pin. Alternate
Functions selected by setting or clearing bits of this register are defined in
Functions
Alternate function selection on port pins must also be enabled as described in
Alternate Function Sub-Registers
PAFS16
PPUE6
R/W
R/W
on page 38.
6
6
0
00H (Ports A-C); 01H (Port D); 04H (Port A of 8-pin device)
–
D Address Register, accessible through the Port A
PAFS15
PPUE5
R/W
R/W
5
5
0
06H
PAFS14
to the Port A–D Address register. Setting the bits in the
PPUE4
07H
R/W
R/W
on page 47
4
4
0
to the Port A–D Address register. The Alternate
(Table
PAFS13
PPUE3
.
R/W
R/W
3
3
0
24) is accessed through the Port A–D
(Table
Z8 Encore! XP
PAFS12
PPUE2
R/W
25) is accessed through the Port
R/W
2
2
0
General-Purpose Input/Output
Product Specification
–
D Control Register
PAFS11
PPUE1
R/W
R/W
1
1
0
®
GPIO Alternate
F082A Series
Port A–D
PAFS10
PPUE0
R/W
R/W
0
0
0
50