C8051F131-GQR Silicon Laboratories Inc, C8051F131-GQR Datasheet
C8051F131-GQR
Manufacturer Part Number
C8051F131-GQR
Description
IC 8051 MCU 128K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F13xr
Specifications of C8051F131-GQR
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
C8051F1x
Core
8051
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
32
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F120DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
64TQFP
Device Core
8051
Family Name
C8051F13x
Maximum Speed
100 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F131-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Analog Peripherals
10-Bit ADC
-
-
-
-
-
-
Two Comparators
Internal Voltage Reference
V
On-Chip JTAG Debug & Boundary Scan
-
-
-
-
-
General Purpose
DD
MONEN
±1 LSB INL; no missing codes
Programmable throughput up to 100 ksps
8 external inputs; programmable as single-ended or differential
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor (±3 °C)
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watchpoints, stack monitor
Inspect/modify memory and registers
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
IEEE1149.1 compliant boundary scan
XTAL1
XTAL2
VREF0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
DGND
DGND
DGND
AGND
VREF
CP0+
CP1+
Monitor/Brown-out Detector
CP0-
CP1-
VDD
VDD
VDD
TCK
TMS
TDO
AV+
RST
TDI
Analog Power
CP0
Digital Power
M
A
U
X
Calibrated Internal
External Oscillator
Monitor
VDD
Oscillator
CP1
JTAG
Logic
Circuit
VREF
SENSOR
TEMP
Circuitry
Prog
Gain
PLL
Boundary Scan
WDT
Debug HW
100 MIPS, 128 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU
100ksps
(10-Bit)
System
Clock
ADC
Reset
Copyright © 2004 by Silicon Laboratories
C
o
8
0
5
1
e
r
External Data
Memory Bus
64x4 byte
128kbyte
256 byte
SFR Bus
FLASH
8kbyte
XRAM
cache
RAM
High-Speed 8051 µC Core
-
-
-
Memory
-
-
-
Digital Peripherals
-
-
-
-
-
-
Clock Sources
-
-
-
Supply Voltage: 3.0 to 3.6 V
-
-
64-Pin TQFP
Temperature Range: –40 to +85 °C
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 100 MIPS throughput with 100 MHz system clock
16 x 16 multiply/accumulate engine (2-cycle)
8448 bytes data RAM
128 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes
are reserved)
External parallel data memory interface
32 port I/O; all are 5 V tolerant
Hardware SMBus™ (I2C™ Compatible), SPI™, and two UART serial
ports available concurrently
Programmable 16-bit counter/timer array with six capture/compare
modules
5 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Real-time clock mode using Timer 3 or PCA
Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation
On-chip programmable PLL: up to 100 MHz
External oscillator: Crystal, RC, C, or Clock
Typical operating current: 50 mA at 100 MHz
Typical stop mode current: 0.4 µA
Timers 0,
Crossbar
SPI Bus
Timer 3/
Port I/O
Latches
Config.
UART0
UART1
SMBus
P0, P1,
Config.
P2, P3
1, 2, 4
PCA
RTC
Address Bus
Bus Control
Data Bus
C
D
T
L
A
d
d
a
a
r
t
O
C
R
S
S
B
A
R
P4 Latch
P5 Latch
P6 Latch
P7 Latch
C8051F131
P0
Drv
P1
Drv
P2
Drv
P3
Drv
DRV
DRV
DRV
DRV
P4
P5
P6
P7
P0.0
P0.7
P1.0/AIN2.0
P1.7/AIN2.7
P2.0
P2.7
P3.0
P3.7
8.9.2004
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C8051F131-GQR Summary of contents
Page 1
... PCA RAM Timers 8kbyte XRAM Timer 3/ 1 RTC P0, P1, P2, P3 External Data Latches Memory Bus C Crossbar Config FLASH 128kbyte e 64x4 byte cache Copyright © 2004 by Silicon Laboratories C8051F131 P0.0 P0 Drv P0 P1.0/AIN2 Drv P1.7/AIN2 P2 Drv P2 P3.0 P3 Drv P3 Latch Bus Control ...
Page 2
... A1 0.05 - 0.15 A2 0.95 - 1.05 b 0.17 0.22 0. 12. 10. 0. 12. 10.00 - Copyright © 2004 by Silicon Laboratories C8051F131 TYP MAX UNITS — 3 — mA 0.6 — — µA 10 — µA 0.4 — µA — 100 MHz 24.5 25.0 MHz — 100 MHz 10 bits — ...