M306N4FGTFP#U0 Renesas Electronics America, M306N4FGTFP#U0 Datasheet - Page 92

MCU 5V 256K T-TEMP PB-FREE 100-Q

M306N4FGTFP#U0

Manufacturer Part Number
M306N4FGTFP#U0
Description
MCU 5V 256K T-TEMP PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/6Nr
Datasheets

Specifications of M306N4FGTFP#U0

Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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2.00 Nov. 10, 2004
2.10 Jun. 24, 2005
2.40 Aug. 25, 2006
Rev.
Date
REVISION HISTORY
44, 45
46, 47
Page
34
35
36
38
39
40
41
42
49
50
19
32
33
34
2
4
1
4
Table 5.6 A/D Conversion Characteristics: "Tolerance Level Impedance" is added.
Table 5.8 Power Supply Circuit Timing Characteristics: "t
Figure 5.2 Power Supply Circuit Timing Diagram is added.
Table 5.10 Memory Expansion Mode and Microprocessor Mode: "t
Table 5.21 Serial I/O: Min. of standard in t
Table 5.23 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)
Table 5.24 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting
and external area access)
Table 5.25 Memory Expansion Mode and Microprocessor Mode (for 2- to 3-wait setting,
external area access and multiplexed bus selection)
Figure 5.4 Timing Diagram (1): "XIN input" is added.
Figures 5.6 and 5.7 Timing Diagram (3) (4): "DB" in Read timing is revised to "DBi".
Figures 5.8 and 5.9 Timing Diagram (5) (6): "DB" in Write timing is revised to "DBi".
Figure 5.11 Timing Diagram (8)
Appendix 1. Package Dimensions: 100P6Q-A is added.
Revised edition issued
* The contents of product are revised. (Normal-ver. is added.)
* Revised parts and revised contents are as follows (except for expressional change).
Table 1.1 Performance outline of M16C/6N Group (M16C/6N4)
Table 1.2 Product List is revised. (Normal-ver. is added.)
Figure 1.2 Type No., Memory Size, and Package:
Figure 4.7 SFR Information (7): NOTE 1 is revised.
Table 5.4 Electrical Characteristics (1)
Table 5.5 Electrical Characteristics (2): Mask ROM (5th item)
Table 5.6 A/D Conversion Characteristics: “Tolerance Level Impedance” is deleted.
Revised edition issued
* Electric Characteristics of Normal-ver. is added.
* Revised parts and revised contents are as follows (except for expressional change).
1.1 Applications: Comment of Normal-ver. is added.
Table 1.2 Product Information
• Max. of Standard in t
• t
• Max. of Standard in t
• t
• t
• Max. of Standard in t
• "ADi/DB" in Read/Write timing is revised to "ADi/DBi".
• Performance outline of Normal-ver. is added.
• "(no): Normal-ver." is added to Characteristics.
• Measuring Condition of V
• “f(XCIN)” is changed to “(f(BCLK)).
• Status of development is revised and NOTES 1 and 2 are added.
d(BCLK-HLDA)
d(BCLK-HLDA)
d(BCLK-HLDA)
is added.
is added.
is added.
d(BCLK-ALE)
d(BCLK-ALE)
d(BCLK-ALE)
A-2
M16C/6N Group (M16C/6N4) Data Sheet
OL
is revised from “L
Description
is revised from "25" to "15".
is revised from "25" to "15".
is revised from "25" to "15".
Summary
su(D-C)
is revised from "30" to "70".
OL
= –200µA” to “L
d(M-L)
" is deleted.
d(BCLK-HLDA)
OL
= 200µA”.
" is deleted.

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