HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 463

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

This LSI includes an on-chip eight-channel direct memory access controller (DMAC). The DMAC
can be used in place of the CPU to perform high-speed data transfers among external devices
equipped with DACK (DMA transfer end notification), external memories, memory-mapped
external devices, and on-chip peripheral modules. Using the DMAC reduces the burden on the
CPU and increases the operating efficiency of this LSI.
11.1
The DMAC has the following features.
• Number of channels: Eight channels
• Address space: Physical address space
• Selection of data length: 8-bit, 16-bit, 32-bit, 64-bit, or 32-byte transfer data length
• Maximum number of transfers: 16 M (16,777,216) transfers
• Selection of DMA mode: External request 2-channel mode or DMABRG mode
• Selection of address mode: Single address mode*
• Selection of transfer requests: External request*
• Selection of bus mode: Cycle steal mode or burst mode
• Selection of priority order: Fixed priority mode or round robin mode
• Channel functions: Different transfer modes (address mode, bus mode, and transfer requests)
• Interrupt request: Interrupt request can be sent to the CPU on completion of data transfer.
Notes: 1. In DMABRG mode, only synchronous DRAM can be specified.
Section 11 Direct Memory Access Controller (DMAC)
2. External request 2-channel mode: DREQ0 (corresponds to channel 0) and DREQ1
3. External request 2-channel mode: Transfer requests cannot be accepted from the
Features
(corresponds to channel 1)
DMABRG mode: DREQ0 to DREQ3 (can be set for all channels)
LCDC, HAC, SSI, and USB.
DMABRG mode: Transfer requests can be accepted from all on-chip peripheral
modules with the DMA transfer request function. (Note that transfer requests from the
LCDC, HAC, SSI, and USB can only be accepted in channel 0.)
can be set for each channel.
or auto-request
2
, requests from on-chip peripheral modules*
1
or dual address mode
Rev. 2.00 Feb. 12, 2010 Page 379 of 1330
REJ09B0554-0200
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