DS89C450-QNL+ Maxim Integrated Products, DS89C450-QNL+ Datasheet

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... DS89C430-ENL+ 16kB Contact factory or replace with DS89C440-xxx DS89C430 or DS89C450. DS89C450-MNL 64kB DS89C450-MNL+ 64kB DS89C450-QNL 64kB DS89C450-QNL+ 64kB DS89C450-ENL 64kB DS89C450-ENL+ 64kB + Denotes a lead(Pb)-free/RoHS-compliant device. Complete Selector Guide appears at end of data sheet. Pin Configurations appear at end of data sheet. APPLICATIONS Data Logging ...

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... Input Low Current, Port 1, 2, and 3 at 0.4V Transition Current from Port 1, 2, and (Note 12) Input Leakage Current, Port 0 in I/O Mode and EA (Note 13) Input Current, Port 0 in Bus Mode (Note 14) RST Pulldown Resistance (Note 13) DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers SYMBOL V V PFW ...

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... RST = 5.5V. Port 0 is floating during reset and when in the logic-high state during I/O mode. Note 14: This port is a weak address holding latch in bus mode. Peak current occurs near the input transition point of the holding latch at approximately 2V. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers to V MIN RST and V overlap, the design of the hardware makes it so this is not possible ...

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... CLCL - 4 0. CLCL CLCL 0.5t CLCL STC3 - CLCL CLCL - 8 0. 0.5t CLCL + STC2 - 8 0. 0.5t CLCL + STC3 CLCL 1. 0.5t CLCL - CLCL CLCL DS89C430/DS89C450 UNITS MIN MAX 0 33 MHz CLCL ns STC3 CLCL CLCL ns STC3 CLCL ns STC2 - 8 CLCL ns STC2 CLCL CLCL ...

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... CLCL CLCL - CLCL CLCL + STC1 STC1 STC1 - CLCL CLCL + STC1 STC1 STC1 CLCL CLCL + STC1 STC1 DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers 4-CYCLE PAGE MODE 2 NONPAGE MODE MAX MIN MAX MIN CLCL CLCL CLCL 1. CLCL 2. CLCL CLCL CLCL CLCL + STC1 - CLCL CLCL + STC1 ...

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... STC2 STC2 0. 1.5t CLCL CLCL - STC5 STC5 - STC2 CLCL STC2 CLCL - STC2 STC2 STC2 STC2 DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers 4-CYCLE PAGE MODE 2 NONPAGE MODE MAX MIN MAX MIN CLCL + t STC1 3. CLCL CLCL STC1 STC1 - 0. 0. 0.5t CLCL CLCL CLCL CLCL ...

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... PXIX LLIV t LLAX Port 0 LSB MOVX t PXIZ Port 2 MSB DS89C430/DS89C450 Ultra-High-Speed Flash Micrcontrollers ” used in the AC Characteristics variable timing table is determined from the CLCL Number of External Clock Cycles per System Clock (1/t ) CLCL 1/4 1/2 Reserved 1 1024 MOVX Instruction Time t STC1 ...

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... Port 2 Figure 3. Page Mode 2 Timing XTAL1 t CLCL ALE t AVLL t AVLL2 PSEN t LLPL t PLIV PXIX t LLIV Port 0 LSB t LLAX Port 2 MSB OPCODE DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers t LHLL t LLAX3 t LLWL t RLRH t RHDX t RLDV MOVX DATA t AVDV2 MSB LSB MSB t LHLL t AVLL3 t PLPH t LLAX3 ...

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... Rising Clock Rising Edge to Input t XHDV Data Valid Note: SM2 is the serial port 0 mode bit 2. When serial port 0 is operating in mode 0 (SM0 = SM1 = 0), SM2 determines the number of crystal clocks in a serial port clock cycle. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers SYMBOL t CHCX t CLCX t ...

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... RXD DATA IN TXD CLOCK t XHDV R1 SERIAL PORT (SYNCHRONOUS MODE) SM2 = 0 TDX CLOCK = XTAL FREQ/12 ALE PSEN WRITE TO SBUF RXD DATA OUT TXD CLOCK TI WRITE TO SCON TXD CLOCK TO CLEAR RI RXD DATA IN TXD CLOCK R1 DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers t XHQX XLXL XHDX 1/(XTAL FREQ/12 ...

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... Note 19: Reset delay is a synchronous counter of crystal oscillations after crystal startup. Counting begins when the level on the XTAL1 pin meets the V criteria. At 33MHz, this time is 1.99ms. IH2 FLASH MEMORY PROGRAMMING CHARACTERISTICS (V = 4.5V to 5.5V) CC PARAMETER Data Retention Write/Erase Endurance Program/Time Erase Time DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers SYMBOL MIN TYP t 8 CSU t 65,536 POR SYMBOL MIN TYP ...

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... P0.5 (AD5) P0.6 (AD6 P0.7 (AD7 DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers NAME V +5V CC GND Logic Ground External Reset. The RST input pin is bidirectional and contains a Schmitt Trigger to recognize external active-high reset inputs. The pin also employs an internal pulldown RST resistor to allow for a combination of wire-ORed external reset sources not required for power-up, as the device provides this function internally ...

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... In this state, a weak pullup holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port overcomes the weak pullup. When software writes any port pin, the DS89C430/DS89C450 activate a strong pulldown that remains on until either written or a reset occurs. Writing a 1 after the port has been at 0 causes a strong transition driver to turn on, followed by a weaker sustaining pullup ...

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... I/O ports. The three part numbers vary only by the amount of internal flash memory (DS89C430 = 16kB, DS89C450 = 64kB), which can be in-system/in- application programmed from a serial port using ROM-resident or user-defined loader software. For volume deployments, the flash can also be loaded externally using standard commercially available parallel programmers ...

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... Terminology The term DS89C430 is used in the remainder of the document to refer to the DS89C430 and DS89C450, unless otherwise specified. Compatibility The DS89C430 is a fully static CMOS 8051-compatible microcontroller similar in functional features to the DS87C520, but it offers much higher performance. In most cases, the DS89C430 can drop into an existing socket for the 8xC51 family, immediately improving the operation ...

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... PCON 87h SMOD_0 TCON 88h TF1 TMOD 89h GATE TL0 8Ah TL1 8Bh TH0 8Ch DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers Table 2 specifies the default reset condition for all SFR BIT 6 BIT 5 BIT 4 P0.6 P0.5 P0.4 ID0 TSL AID SMOD0 OFDF OFDE TR1 ...

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... WDCON D8h SMOD_1 ACC E0h EIE E8h — B F0h EIP1 F1h — EIP0 F8h — Note: Shaded bits are timed-access protected. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers BIT 6 BIT 5 BIT 4 WD0 T2M T1M P1.6/INT4 P1.5/INT3 P1.4/INT2 IE4 IE3 IE2 T2MH T1MH SM1_0 SM2_0 ...

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... A9h SADDR1 AAh P3 B0h IP1 B1h IP0 B8h SADEN0 B9h SADEN1 BAh SCON1 C0h SBUF1 C1h ROMSIZE C2h PMR C4h STATUS C5h TA C7h T2CON C8h T2MOD C9h RCAP2L CAh RCAP2H CBh DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers BIT 7 BIT 6 BIT 5 BIT Special Special ...

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... The registers are located on-chip but the program and data memory spaces can be on-chip, off-chip, or both. The DS89C430/DS89C450 have 16kB/64kB of on-chip program memory, respectively, implemented in flash memory and also have 1kB of on-chip data memory space that can be configured as program space using the PRAME bit in the ROMSIZE feature ...

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... SRAM for on-chip data memory or a particular range (400–7FF) of “alternate” program memory space. The DS89C450 incorporates two 32kB flash memories. The DS89C430 uses an address scheme that separates program memory from data memory such that the 16-bit address bus can address each memory area up to maximum of 64kB ...

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... On-chip program memory begins at address 0000h and is contiguous through 3FFFh (16kB) on the DS89C430 and through FFFFh (64kB) on the DS89C450. Exceeding the maximum address of on-chip program memory causes the device to access off-chip memory. The maximum on-chip decoded address is selectable by software using the ROMSIZE feature ...

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... The value of this register can be read at address FCh in parallel programming mode or executing a verify-option-control register instruction in ROM loader mode or in- application programming mode. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers supply under the control of the user software or by using a built-in program CC ...

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... The flash command (FC3–FC0;FCNTL.3:0) bits provide flash commands as listed in DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers MEANING Manufacturer ID DS89C430 Device ID DS89C440 Device ID (Contact factory or replace with DS89C430 or DS89C450.) DS89C450 Device ID Device Extension rite upper program memory bank " is shown below. The command must be Table 4 ...

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... Any command written to the FCNTL during a flash operation is ignored (FBUSY = 0). To ensure data integrity, an erase command sequence should be reinitiated if an erase or program operation is interrupted by a reset. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers OPERATION Default state. All flash blocks are in read mode. Note: The upper bank of flash memory is inaccessible for execution unless the FC3:0 bits are in the read mode (0000b) state ...

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... ID1 and ID0 bits. This option is enabled by setting the automatic increment/decrement enable (AID–DPS. logic 1 and is affected by the following three instructions: MOVC A, @A+DPTR MOVX A, @DPTR MOVX @DPTR, A Windows is a registered trademark of Microsoft Corporation. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers ID0 SEL = 0 SEL = 1 0 INC DPTR ...

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... PSEN is only asserted for external code fetches, and is inactive during internal execution. Figure 7. External Program Memory Access (Nonpage Mode, CD1:CD0 = 10) Internal Memory Cycles XTAL1 ALE PSEN Port 0 Port 2 DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers External Memory Cycle External Memory Cycle LSB Add ...

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... The following diagrams illustrate the timing relationship for external data memory access in full speed (stretch value = 0), in the default stretch setting (stretch value = 1), and slow data memory accessing (stretch value = 4), when the system clock is in divide-by-1 mode (CD1:CD0 = 10b). DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers RD/WR PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS) 4X/2X, CD1, CD0 = 000 0 ...

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... Figure 9. Nonpage Mode, External Data Memory Access (Stretch = 1, CD1:CD2 = 10) 1st Machine Cycle XTAL1 ALE PSEN RD/WR Port 0 A MOVX Port 2 A MOVX Instruction Fetch DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers MOVX Instruction 2nd Machine Cycle 1st Machine Cycle A INST A DATA A Memory Access Stretch = 0 MOVX Instruction 2nd Machine Cycle ...

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... During a page hit, P2 drives Addr [0–7] of the 16-bit address, while the most significant address byte is held in the external address latches. PSEN, RD, and WR strobes accordingly for the appropriate operation on the P0 data bus. There is no ALE assertion for page hits. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers EXTERNAL BUS STRUCTURE PAGE-MISS P0: Primary data bus ...

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... Generally, the first external memory access causes a page miss. The new page address is stored internally and is used to detect a page miss for the current external memory cycle. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers External Memory Cycles MOVX MOVX ...

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... MOVX memory bus cycle and the control signals’ pulse width in terms of the number of oscillator clocks. A stretch machine cycle always contains four system clocks, independent of the logic value of the page mode select bits. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers illustrates the memory cycle for external code fetches. Page Miss ...

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... STRETCH MD2:MD0 4X CD1, CYCLES 000 0 001 1 010 2 011 3 100 7 101 8 110 9 111 10 DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS) 4X CD1, CD0 = 100 CD0 = 000 0.25 0.5 0.75 1.5 1.75 3.5 2.75 5.5 3.75 7.5 4.75 9.5 5.75 11.5 6.75 13 ...

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... The stretched data memory bus cycle timing relationship for PAGES = 11 is identical to nonpage mode operation since the basic data memory cycle always contains four system clocks in this page mode operation. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers RD/WR PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS) 4X CD1, ...

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... MOVX Inst Fetch ALE PSEN Port 0 Inst MOVX Port 2 LSB Addr LSB Addr MOVX Inst Fetch DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers MOVX Instruction Inst MOVX LSB Addr LSB Addr MSB Addr Memory Access (Stretch =1) MOVX Instruction Inst LSB Addr LSB Addr MSB Addr ...

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... The power-fail interrupt is controlled by its individual enable only. The interrupt enables and priorities are functionally identical to those of the 80C52, except that the DS89C430 supports five levels of interrupt priorities instead of the original two. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers MOVX Instruction (Page miss) 1st ...

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... Note 1: If the interrupt is edge triggered, the flag is cleared automatically by hardware when the service routine is vectored to. If the interrupt is level triggered, the flag follows the state of the pin. Note 2: The flag is cleared automatically by hardware when the service routine is vectored to. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers FLAG 0 (Highest) PFI (WDCON ...

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... Before these bits can be altered, the processor must execute the timed-access sequence. This sequence consists of writing an AAh to the timed access (TA, C7h) register, followed by writing a 55h to the same register within three machine cycles. This timed sequence of steps allows any of the timed access-protected SFR bits to be altered DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers TIMER 0 TIMER 1 ...

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... Figure 14 gives a simplified description of the generation of the system clocks. Specifics of hardware restrictions associated with the use of the 4X/2X CTM, CKRY, CD1, and CD0 bits are outlined in the SFR section. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers ...

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... BGS (EXIF.0) bit is set to logic 0. This is the lowest power mode. If BGS is set to logic 1, the bandgap reference, reset comparator, and the power-fail comparator are powered up, although in a mode that reduces their power consumption. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers 4X/2X CTM ...

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... A software reset can be initiated by writing a system reset command to the flash control SFR. The reset state is maintained for approximately 90 external clock cycles. During this time, the RST pin is driven to a logic high. Once the reset is removed, the RST pin is driven low, and operation begins from address 0000h. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers WD1 ...

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... The basic divide-by-12 mode for the timers (TxMH, TxM = 00b) as well as the divide by 32 and 64 for mode 2 on the serial ports has been maintained when running the processor with the oscillator divide ratio of 0.25, 0.5, and 1. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers ...

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... On returning from the interrupt vector using the RETI instruction, the next address is the one that immediately follows the instruction that invoked the idle mode. Any reset of the processor also removes the idle mode. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers summarizes the effect of clock mode on timer operation. OSC CYCLES PER ...

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... There are some special conditions and features to be considered when analyzing the DS89C430 instruction set. Full details are available in the Ultra-High-Speed Flash Microcontroller User’s Guide. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers should drop below the V CC ...

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... DS89C430-ENG+ -40°C to +85°C DS89C440-xxx DS89C450-MNL -40°C to +85°C DS89C450-MNL+ -40°C to +85°C DS89C450-QNL -40°C to +85°C DS89C450-QNL+ -40°C to +85°C DS89C450-ENL -40°C to +85°C DS89C450-ENL+ -40°C to +85°C DS89C450-MNG -40°C to +85°C DS89C450-MNG+ -40°C to +85°C DS89C450-QNG -40° ...

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... DS89C430 DS89C450 44 1 TQFP PACKAGE INFORMATION For the latest package outline information and land patterns www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE 44 TQFP C44+2 40 PDIP P40+3 40 PLCC Q44+7 DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers 40 39 P1.0/T2 P1.1/T2EX P1.2/RXD1 P1.3/TXD1 P1.4/INT2 P1.5/INT3 29 P1.6/INT4 P1.7/INT5 28 RST P3.0/RXD0 P3 ...

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... Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers DESCRIPTION © ...