PIC16C74-10/P Microchip Technology, PIC16C74-10/P Datasheet - Page 23

• Manufacturer Part Number: PIC16C74-10/P
• Description: MICRO CTRL 4K 10MHZ OTP 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C74-10/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

4.2.2
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
TABLE 4-1:
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Note 1: These registers can be addressed from either bank.
Address Name
1997 Microchip Technology Inc.
Bank 0
(1)
(1)
(1)
(1)
(1,2)
(1)
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC16C72, always maintain these bits clear.
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
ADRES
ADCON0
SPECIAL FUNCTION REGISTERS
Shaded locations are unimplemented, read as ‘0’.
contents are transferred to the upper byte of the program counter.
—
—
—
—
—
—
—
—
—
PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
Unimplemented
Unimplemented
Unimplemented
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
Timer2 module’s register
Synchronous Serial Port Receive Buffer/Transmit Register
Capture/Compare/PWM Register (LSB)
Capture/Compare/PWM Register (MSB)
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
A/D Result Register
ADCS1
WCOL
IRP
Bit 7
GIE
—
—
—
—
—
—
(4)
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0
SSPOV
ADCS0
RP1
PEIE
ADIF
Bit 6
—
—
—
—
(4)
PORTA Data Latch when written: PORTA pins when read
T1CKPS1
SSPEN
CCP1X
CHS2
Bit 5
T0IE
RP0
—
—
Write Buffer for the upper 5 bits of the Program Counter
T1CKPS0 T1OSCEN
CCP1Y
CHS1
INTE
Bit 4
CKP
TO
—
CCP1M3
SSPM3
SSPIF
CHS0
RBIE
Bit 3
PD
The special function registers can be classified into two
sets (core and peripheral). Those registers associated
with the “core” functions are described in this section,
and those related to the operation of the peripheral fea-
tures are described in the section of that peripheral fea-
ture.
GO/DONE
TMR2ON
T1SYNC
CCP1M2
CCP1IF
SSPM2
Bit 2
T0IF
Z
T2CKPS1
TMR1CS
CCP1M1
TMR2IF
SSPM1
Bit 1
INTF
DC
—
T2CKPS0 -000 0000 -000 0000
TMR1ON
CCP1M0
TMR1IF
SSPM0
ADON
Bit 0
RBIF
C
PIC16C7X
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--0x 0000 --0u 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---0 0000 ---0 0000
0000 000x 0000 000u
-0-- 0000 -0-- 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --uu uuuu
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
xxxx xxxx uuuu uuuu
0000 00-0 0000 00-0
Value on:
POR,
BOR
DS30390E-page 23
—
—
—
—
—
—
—
—
—
other resets
Value on all
(3)
—
—
—
—
—
—
—
—
—