AT90LS8535-4AC Atmel, AT90LS8535-4AC Datasheet - Page 45

• Manufacturer Part Number: AT90LS8535-4AC
• Description: IC MCU 8K 4MHZ A/D LV 44TQFP
• Manufacturer: Atmel
• Series: AVR® 90LSr

Specifications of AT90LS8535-4AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Timer/Counter2 in PWM Mode
1041H–11/01
When the PWM mode is selected, Timer/Counter2 and the Output Compare Register
(OCR2) form an 8-bit, free-running, glitch-free and phase correct PWM with outputs on
the PD7(OC2) pin. Timer/Counter2 acts as an up/down counter, counting up from $00 to
$FF, where it turns and counts down again to zero before the cycle is repeated. When
the counter value matches the contents of the Output Compare Register, the PD7(OC2)
pin is set or cleared according to the settings of the COM21/COM20 bits in the
Timer/Counter2 Control Register (TCCR2). Refer to Table 19 for details.
Table 19. Compare Mode Select in PWM Mode
Note that in PWM mode, the Output Compare Register is transferred to a temporary
location when written. The value is latched when the Timer/Counter reaches $FF. This
prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsyn-
chronized OCR2 write. See Figure 35 for an example.
Figure 35. Effects of Unsynchronized OCR Latching
During the time between the write and the latch operation, a read from OCR2 will read
the contents of the temporary location. This means that the most recently written value
always will read out of OCR2.
When the OCR register (not the temporary register) is updated to $00 or $FF, the PWM
output changes to low or high immediately according to the settings of COM21/COM20.
This is shown in Table 20.
Table 20. PWM Outputs OCR2 = $00 or $FF
COM21
0
0
1
1
COM21
1
COM20
Compare Value changes
0
1
0
1
Effect on Compare Pin
Not connected
Not connected
Cleared on compare match, up-counting. Set on compare match, down-
counting (non-inverted PWM).
Cleared on compare match, down-counting time-out. Set on compare
match, up-counting (inverted PWM).
Compare Value changes
Unsynchronized OCR Latch
Synchronized OCR Latch
COM20
0
OCR2
$00
Glitch
AT90S/LS8535
Output PWM2
Counter Value
Compare Value
PWM Output
Counter Value
Compare Value
PWM Output
L
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