AT90S2333-8PC Atmel, AT90S2333-8PC Datasheet

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... PDIP and 32-pin TQFP • Operating Voltage – 2.7V - 6.0V (AT90LS2333 and AT90LS4433) – 4.0V - 6.0V (AT90S2333 and AT90S4433) • Speed Grades – MHz (AT90LS2333 and AT90LS4433) – MHz (AT90S2333 and AT90S4433) Pin Configurations TQFP Top View (INT1) PD3 1 24 PC1 (ADC1) (T0) PD4 ...

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... SPI serial interface conventional nonvolatile memory programmer. By combining a RISC 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT90S2333/4433 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. ...

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... Block Diagram Figure 1. The AT90S2333/4433 Block Diagram VCC GND AVCC ANALOG MUX AGND AREF PROGRAM COUNTER PROGRAM FLASH INSTRUCTION REGISTER INSTRUCTION DECODER CONTROL LINES PROGRAMMING LOGIC DATA REGISTER PORTB AT90S/LS2333 and AT90S/LS4433 PC0 - PC5 PORTC DRIVERS DATA REGISTER DATA DIR. PORTC REG ...

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... Port D pins that are externally pulled low will source current if the pull-up resistors are activated. Port D also serves the functions of various special features of the AT90S2333/4433 as listed on page 67. The port D pins are tristated when a reset condition becomes active, even if the clock is not running. ...

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Clock Options Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be configured for use as an on- chip oscillator, as shown in Figure 2 and Figure 3. Either a quartz crystal or ...

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... The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 5 shows the AT90S2333/4433 AVR RISC microcontroller architecture. In addition to the register operation, the conventional memory addressing modes can be used on the register file as well. ...

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... The 128 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. Figure 6. AT90S2333/4433 Memory Maps Program Memory Program Flash A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register ...

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General Purpose Register File Figure 7 shows the structure of the 32 general purpose working registers in the CPU. Figure 7. AVR CPU General Purpose Working Registers 7 General Purpose Working Registers All the register operating instructions in the instruction ...

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... Flash is organized as 1K/2K x 16. The Flash memory has an endurance of at least 1000 write/erase cycles. The AT90S2333/4433 Program Counter (PC) is 10/11 bits wide, thus addressing the 1024/2048 program memory addresses. See page 78 for a detailed description on Flash data downloading. See page 10 for the different program memory addressing modes ...

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... See the next section for a detailed description of the different addressing modes. Program and Data Addressing Modes The AT90S2333/4433 AVR RISC microcontroller supports powerful and efficient addressing modes for access to the Flash program memory, SRAM, Register File, and I/O data memory. This section describes the different addressing modes sup- ported by the AVR architecture ...

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I/O Direct Figure 12. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word the destination or source register address. Data Direct Figure 13. Direct Data Addressing A 16-bit Data Address is contained in ...

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Data Indirect Figure 15. Data Indirect Addressing 15 Operand address is the contents of the the Z-register. Data Indirect with Pre-Decrement Figure 16. Data Indirect Addressing with Pre-Decrement 15 The the Z-register is decremented ...

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Constant Addressing Using the LPM Instruction Figure 18. Code Memory Constant Addressing Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 1K/2K), the LSB selects low byte if cleared (LSB = 0) ...

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... EEPROM Data Memory The AT90S2333/4433 contains 128/256 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles per location. The access between the EEPROM and the CPU is described on page 44 specifying the EEPROM address regis- ters, the EEPROM data register, and the EEPROM control register ...

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... Figure 23. On-Chip Data SRAM Access Cycles System Clock Ø Address I/O Memory The I/O space definition of the AT90S2333/4433 is shown in the following table: Table 2. AT90S2333/4433 I/O Space I/O Address (SRAM Address) Name $3F ($5F) SREG $3D ($5D) SP $3B ($5B) GIMSK $3A ($5A) GIFR $39 ($59) TIMSK $38 ($58) ...

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... Reserved and unused locations are not shown in the table. All AT90S2333/4433 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions ...

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... Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. Stack Pointer - SP The AT90S2333/4433 Stack Pointer is implemented as an 8-bit register in the I/O space location $3D ($5D). As the AT90S2333/4433 data memory has $0DF locations, 8 bits are used. $3D ($5D) ...

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... RETI. Reset and Interrupt Handling The AT90S2333/4433 provides 13 different interrupt sources. These interrupts and the separate reset vector, each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be set (one) together with the I-bit in the status register in order to enable the interrupt. ...

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... Reset Sources The AT90S2333/4433 has four sources of reset: • Power-On Reset. The MCU is reset when the supply voltage is below the power-on reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for more than 50 ns. ...

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Table 5. Reset Delay Selections CKSEL [2:0] Start-Up Time, t TOUT 000 001 6 CK 010 256 ms + 16K CK 011 16K CK 100 16K CK 101 256 ...

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... Figure 27. External Reset During Operation Brown-Out Detection AT90S2333/4433 has an on-chip brown-out detection (BOD) circuit for monitoring the V power supply must be decoupled with 100 nF capacitor if the BOD function is used. The BOD circuit can be enabled/disabled by the fuse BODEN. When BODEN is enabled (BODEN programmed), and V below the trigger level, the brown-out reset is immediately activated ...

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... Bits 7..4 - Res: Reserved Bits These bits are reserved bits in the AT90S2333 and always read as zero. • Bit 3 - WDRF: Watchdog Reset Flag This bit is set if a watchdog reset occurs. The bit is cleared by a power-on reset writing a logic zero to the flag. ...

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... Interrupt Handling The AT90S2333/4433 has two 8-bit Interrupt Mask control registers; GIMSK - General Interrupt Mask register and TIMSK - Timer/Counter Interrupt Mask register. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user soft- ware can set (one) the I-bit to enable nested interrupts ...

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... The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. • Bit 0 - Res: Reserved bit This bit is a reserved bit in the AT90S2333/4433 and always reads as zero. AT90S/LS2333 and AT90S/LS4433 24 5 ...

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... Bit 0 - Res: Reserved bit This bit is a reserved bit in the AT90S2333/4433 and always reads as zero. External Interrupts The external interrupts are triggered by the INT1 and INT0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0/INT1 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level ...

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... Bits Res: Reserved bit These bits are reserved bits in the AT90S2333/4433 and always reads as zero. • Bit 5 - SE: Sleep Enable The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction ...

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The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If ...

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... Timer / Counters The AT90S2333/4433 provides two general purpose Timer/Counters - one 8-bit T/C and one 16-bit T/C. Timer/Counters 0 and 1 have individual prescaling selection from the same 10-bit prescaling timer. These Timer/Counters can either be used as a timer with an internal clock timebase counter with an external pin connection which triggers the counting. ...

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... Bits 7-3 - Res: Reserved bits These bits are reserved bits in the AT90S2333/4433 and always read as zero. • Bits 2,1,0 - CS02, CS01, CS00: Clock Select0, bit 2,1 and 0 The Clock Select0 bits 2,1, and 0 define the prescaling source of Timer0. Table 9. Clock 0 Prescale Select ...

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Timer Counter 0 - TCNT0 Bit 7 6 $32 ($52) MSB Read/Write R/W R/W Initial value 0 0 The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is ...

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When Timer/Counter1 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU ...

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... Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP. • Bits Res: Reserved bits These bits are reserved bits in the AT90S2333/4433 and always read zero. • Bit 3 - CTC1: Clear Timer/Counter1 on Compare match When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compare match. If the CTC1 control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match ...

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Table 12. Clock 1 Prescale Select CS12 CS11 CS10 The Stop condition provides a Timer Enable/Disable ...

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Timer/Counter1 Output Compare Register - OCR1H and OCR1L Bit 15 14 $2B ($4B) MSB $2A ($4A Read/Write R/W R/W R/W R/W Initial value The output compare register is a 16-bit read/write register. The Timer/Counter1 ...

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COM11 and COM10 bits in the Timer/Counter1 Control Register TCCR1. Refer to Table 14 for details. Table 13. Timer TOP Values and PWM Frequency PWM Timer TOP Resolution value 8-bit ...

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... The WDR - Watchdog Reset - instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog reset, the AT90S2333/4433 resets and executes from the reset vector. For timing details on the Watchdog reset, refer to page 22. ...

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Bit 3 - WDE: Watch Dog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE ...

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... Bit 7..4 - Res: Reserved bits These bits are reserved bits in the AT90S2333/4433 and will always read as zero. • Bit 3 - EERIE: EEPROM Ready Interrupt Enable When the I bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the inter- rupt is disabled. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared (zero). • ...

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Bit 1 - EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into ...

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... Serial Peripheral Interface - SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90S2333/4433 and peripheral devices or between several AVR devices. The AT90S2333/4433 SPI features include the following: • Full-Duplex, 3-Wire Synchronous Data Transfer • Master or Slave Operation • ...

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Figure 37. SPI Master-Slave Interconnection The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift ...

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Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 38 and Figure 39. Figure 38. ...

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... Bit 5..0 - Res: Reserved bits These bits are reserved bits in the AT90S2333/4433 and will always read as zero. The SPI interface on the AT90S2333/4433 is also used for program memory and EEPROM downloading or uploading. See page 78 for serial programming and verification. SPI Data Register - SPDR ...

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... UART The AT90S2333/4433 features a full duplex (separate receive and transmit registers) Universal Asynchronous Receiver and Transmitter (UART). The main features are: • Baud rate generator generates any baud rate • High baud rates at low XTAL frequencies • bits data • Noise filtering • ...

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A new character has been written to UDR before the stop bit from the previous character has been shifted out. The shift register is loaded when the stop bit of the character currently being transmitted has been shifted out. ...

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The receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate. While the line is idle, one single sample of logical zero will be interpreted as the falling edge of a start ...

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Each slave MCU reads the UDR register and determines if it has been selected. If so, it clears the MPCM bit in UCSRA, otherwise it waits for the next address byte. 4. For each received data byte, the receiving ...

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... The OR bit is cleared (zero) when data is received and transferred to UDR. • Bits 2..1 - Res: Reserved bits These bits are reserved bits in the AT90S2333/4433 and will always read as zero. • Bit 0 - MPCM: Multi-Processor Communication Mode This bit is used to enter Multi-Processor Communication Mode. The bit is set when the slave MCU waits for an address byte to be received. When the MCU has been addressed, the MCU switches off the MPCM bit, and starts data reception. For a detailed description, see “ ...

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For standard crystal frequencies, the most commonly used baud rates can be generated by using the UBR settings in Table 19. UBR values which yield an actual baud rate differing less than 2% from the target baud rate, are bold ...

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UART Baud Rate Register - UBRR Bit 15 14 $03 ($23 $09 ($29) MSB 7 6 Read/Write R R R/W R/W Initial value This is a 12-bit register which contains the UART Baud Rate ...

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Bit 6 - AINBG: Analog Comparator Bandgap Select When this bit is set BOD is enabled and the BODEN is programmed, a fixed bandgap voltage of 1.22 ± 0.05V replaces the normal input to the positive input (AIN0) of ...

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... Interrupt on ADC conversion complete. • Sleep Mode Noise Canceler The AT90S2333/4433 features a 10-bit successive approximation ADC. The ADC is connected to a 6-channel Analog Mul- tiplexer which allows each pin of Port used as an input for the ADC. The ADC contains a Sample and Hold Amplifier which ensures that the input voltage to the ADC is held at a constant level during conversion ...

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The ADC is enabled by writing a logical one to the ADC Enable bit, ADEN in ADCSR. The first conversion that is started after enabling the ADC, will be preceded by a dummy conversion to initialize the ADC. To the ...

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Figure 46. ADC Timing Diagram, First Conversion (Single Conversion Mode) Cycle number 1 2 ADC clock ADEN ADSC Hold strobe ADIF ADCH ADCL Dummy Conversion Table 21. ADC Conversion Time Condition Sample Cycle Number 1st Conversion, Free Run 1st Conversion, ...

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... ADC. • Bit 5..3 - Res: Reserved Bits These bits are reserved bits in the AT90S2333/4433, and should be written to zero if accessed. • Bits 2..0 - MUX2..MUX0: Analog Channel Select Bits 2-0 The value of these three bits selects which analog input 5-0 is connected to the ADC. ...

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ADC Control and Status Register - ADCSR Bit 7 6 $06 ($26) ADEN ADSC Read/Write R/W R/W Initial value 0 0 • Bit 7 - ADEN: ADC Enable Writing a logical ‘1’ to this bit enables the ADC. By clearing ...

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... If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. The analog part of the AT90S2333/4433 and all analog components in the application should have a separate analog ground plane on the PCB. This ground plane is connected to the digital ground plane via a single point on the PCB. ...

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Figure 49. ADC Power Connections Note that since AV feeds the Port C output drivers, the RC network shown should not be employed if any Port C serve as CC outputs. ADC Characteristics - ...

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I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direc- tion of one port pin can be changed without unintentionally changing the direction of any other pin with the ...

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The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading ...

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Figure 50. Port B Schematic Diagram (Pin PB0) PB0 WP: WD: RL: RP: RD: ACIC: ACO: Figure 51. Port B Schematic Diagram (Pin PB1) PB1 AT90S/LS2333 and AT90S/LS4433 MOS PULL WRITE PORTB WRITE DDRB NOISE CANCELER ...

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Figure 52. Port B Schematic Diagram (Pin PB2) PB2 WP: WD: RL: RP: RD: MSTR: SPE: Figure 53. Port B Schematic Diagram (Pin PB3) PB3 WP: WD: RL: RP: RD: SPE: MSTR AT90S/LS2333 and AT90S/LS4433 62 MOS PULL ...

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Figure 54. Port B Schematic Diagram (Pin PB4) PB4 WP: WD: RL: RP: RD: SPE: MSTR Figure 55. Port B Schematic Diagram (Pin PB5) PB5 WP: WD: RL: RP: RD: SPE: MSTR AT90S/LS2333 and AT90S/LS4433 MOS PULL- UP WRITE PORTB ...

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Port C Port 6-bit bi-directional I/O port. Three I/O memory address locations are allocated for the Port C, one each for the Data Register - PORTC, $15($35), Data Direction Register - DDRC, $14($34) and the Port C ...

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Table 25. DDCn Effects on Port C Pins DDCn PORTCn Note: n: 5…0, pin number Port C Schematics Note that all port pins are synchronized. The synchronization latch is however, not shown ...

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Table 26. Port D Pins Alternate Functions Port Pin Alternate Function PD0 RXD (UART Input line) PD1 TXD (UART Output line) PD2 INT0 (External interrupt 0 input) PD3 INT1 (External interrupt 1 input) PD4 T0 (Timer/Counter 0 external counter input) ...

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Table 27. DDDn Bits on Port D Pins DDDn PORTDn Note: n: 7,6…0, pin number. Alternate Functions Of Port D • AIN1 - Port D, Bit 7 AIN1, Analog Comparator Negative Input. ...

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Port D Schematics Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures. Figure 57. Port D Schematic Diagram (Pin PD0) PD0 Figure 58. Port D Schematic Diagram (Pin PD1) PD1 AT90S/LS2333 and ...

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Figure 59. Port D Schematic Diagram (Pins PD2 and PD3) Figure 60. Port D Schematic Diagram (Pins PD4 and PD5) PDn AT90S/LS2333 and AT90S/LS4433 WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ ...

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Figure 61. Port D Schematic Diagram (Pins PD6 and PD7) PDn PWRDN: POWER DOWN MODE AT90S/LS2333 and AT90S/LS4433 70 MOS PULL PWRDN RP WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: ...

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... Memory Programming Program and Data Memory Lock Bits The AT90S2333/4433 MCU provides two Lock bits which can be left unprogrammed (‘1’) or can be programmed (‘0’) to obtain the additional features listed in Table 28. The Lock bits can only be erased with the Chip Erase command. ...

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... Fuse bits in the AT90S2333/4433. Signal Names In this section, some pins of the AT90S2333/4433 are referenced by signal names describing their function during parallel programming. See Figure 62 and Table 30. Pins not described in Table 30 are referenced by pin names. The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding are shown in Table 31 ...

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Table 30. Pin Name Mapping Signal Name in Programming Mode RDY/BSY XA0 XA1 DATA Table 31. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low ...

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Set XA1, XA0 to ‘10’. This enables command loading. 2. Set BS to ‘0’. 3. Set DATA to ‘1000 0000’. This is the command for Chip erase. 4. Give XTAL1 a positive pulse. This loads the command. 5. Give ...

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Address high byte needs only be loaded before programming a new 256 word page in the Flash. • Skip writing the data value $FF, that is the contents of the entire Flash and EEPROM after a Chip Erase. These ...

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Programming the EEPROM The programming algorithm for the EEPROM data memory is as follows (refer to Programming the Flash for details on Command, Address and Data loading Load Command ‘0001 0001’ Load Address Low Byte ($00 ...

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Bit 5 = SPIEN Fuse bit Bit 4 = BODLEVEL Fuse bit Bit 3 = BODEN Fuse bit Bit 2 = CKSEL2 Fuse bit Bit 1 = CKSEL1 Fuse bit Bit 0 = CKSEL0 Fuse bit 3. Set BS to ...

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... AT90S/LS2333 and AT90S/LS4433 ± 10 Min 11 (1) 67 (2) (2) 0 1.0 for Programming the Fuse Bits. t WLWH_PFB , no RDY/BSY pulse will be seen. t WLRH AT90S2333/4433 DATA OUT PB4(MISO) INSTR. IN PB3(MOSI) CLOCK IN PB5(SCK) GND RESET XTAL2 MHz XTAL1 GND =5V ± 10% Typ Max 12.5 250 20 0.7 0 1.5 1.8 +2 ...

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... Serial Programming Algorithm When writing serial data to the AT90S2333/AT90S4433, data is clocked on the rising edge of CLK. When reading data from the AT90S2333/AT90S4433, data is clocked on the falling edge of CLK. See Figure 67, Figure 68 and Table 36 for details. To program and verify the AT90S2333/AT90S4433 in the serial programming mode, the following sequence is recom- mended (See four byte instruction formats in Table 35): 1 ...

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Data Polling EEPROM When a byte is being programmed into the EEPROM, reading the address location being programmed will give the value P1 until the auto-erase is finished, and then the value P2. See Table 34 for P1 and P2 ...

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Table 35. Serial Programming Instruction Set Instruction Byte 1 1010 1100 Programming Enable 1010 1100 Chip Erase 0010 H000 Read Program Memory 0100 H000 Write Program Memory Read EEPROM 1010 0000 Memory Write EEPROM 1100 0000 Memory 1010 1100 Write ...

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Serial Programming Characteristics Figure 68. Serial Programming Timing Table 36. Serial Programming Characteristics 2.7 - 6.0V (Unless otherwise noted Symbol Parameter 1/t Oscillator Frequency (V CLCL t Oscillator Period ...

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Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. - +125 C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-1. Voltage on RESET with respect to Ground......-1.0V to +13.0V ...

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DC Characteristics 2.7V to 6.0V (unless otherwise noted) (Continued Symbol Parameter Analog Comparator Input V ACIO Offset Voltage Analog Comparator Input I ACLK Leakage A Analog Comparator t ACPD ...

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External Clock Drive Waveforms Figure 69. External Clock VIH1 VIL1 Table 39. External Clock Drive Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time ...

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Typical Characteristics The following charts show typical behavior. These data are characterized, but not tested. All current consumption measure- ments are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail ...

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Figure 71. Active Supply Current vs Figure 72. Idle Supply Current vs. Frequency AT90S/LS2333 and AT90S/LS4433 CC ...

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Figure 73. Idle Supply Current vs 2.5 Figure 74. Power Down Supply Current vs 2.5 AT90S/LS2333 and AT90S/LS4433 88 CC IDLE SUPPLY CURRENT ...

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Figure 75. Power Down Supply Current vs. V 120 100 Figure 76. Power Down Supply Current vs. V AT90S/LS2333 and AT90S/LS4433 CC POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 2.5 3 3.5 ...

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Figure 77. Analog Comparator Current vs. V 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 Analog comparator offset voltage is measured as absolute offset Figure 78. Analog Comparator Offset Voltage vs. Common Mode Voltage AT90S/LS2333 and AT90S/LS4433 ...

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Figure 79. Analog Comparator Offset Voltage vs. Common Mode Voltage Figure 80. Analog Comparator Input Leakage Current -10 0 0.5 AT90S/LS2333 and AT90S/LS4433 ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Common Mode ...

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Figure 81. Watchdog Oscillator Frequency vs. V AT90S/LS2333 and AT90S/LS4433 92 CC WATCHDOG OSCILLATOR FREQUENCY vs ( ˚ ˚ A ...

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Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 82. Pull-Up Resistor Current vs. Input Voltage Figure 83. Pull-Up Resistor Current vs. Input Voltage AT90S/LS2333 and AT90S/LS4433 PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE ...

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Figure 84. I/O Pin Sink Current vs. Output Voltage Figure 85. I/O Pin Source Current vs. Output Voltage AT90S/LS2333 and AT90S/LS4433 94 I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE ˚ ...

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Figure 86. I/O Pin Sink Current vs. Output Voltage Figure 87. I/O Pin Source Current vs. Output Voltage AT90S/LS2333 and AT90S/LS4433 I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE ˚ ...

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Figure 88. I/O Pin Input Threshold Voltage vs. V Figure 89. I/O Pin Input Hysteresis vs. V AT90S/LS2333 and AT90S/LS4433 96 CC I/O PIN INPUT THRESHOLD VOLTAGE vs ˚ I/O PIN ...

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Register Summary Address Name Bit 7 $3F ($5F) SREG I $3E ($5E) Reserved - $3D ($5D) SP SP7 $3C ($5C) Reserved $3B ($5B) GIMSK INT1 $3A ($5A) GIFR INTF1 $39 ($59) TIMSK TOIE1 $38 ($58) TIFR TOV1 $37 ($57) Reserved ...

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Register Summary (Continued) Address Name Bit 7 $02 ($22) Reserved $01 ($21) Reserved $00 ($20) Reserved Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. ...

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Instruction Set Summary Mnemonics Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...

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Instruction Set Summary (Continued) Mnemonics Operands Description DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers LDI Rd, K Load Immediate LD Rd, X Load Indirect LD Rd, X+ Load Indirect and Post-Inc Load Indirect and ...

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... Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) AT90S/LS2333 and AT90S/LS4433 Ordering Code Package AT90LS2333-4AC 32A AT90LS2333-4PC 28P3 AT90LS2333-4AI 32A AT90LS2333-4PI 28P3 AT90S2333-8AC 32A AT90S2333-8PC 28P3 AT90S2333-8AI 32A AT90S2333-8PI 28P3 AT90LS4433-4AC 32A AT90LS4433-4PC 28P3 AT90LS4433-4AI 32A AT90LS4433-4PI 28P3 AT90S4433-8AC ...

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Packaging Information 28P3, 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) AT90S/LS2333 and AT90S/LS4433 102 32A, 32-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) Dimensions in Millimeters and (Inches) PIN 1 ID ...

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... No licenses to patents or other intellectual prop- erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life suppor t devices or systems. ...