AT90S8535-8AC Atmel, AT90S8535-8AC Datasheet - Page 27

• Manufacturer Part Number: AT90S8535-8AC
• Description: IC MCU 8K FLSH 8MHZ A/D 44TQFP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S8535-8AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Timer/Counter Interrupt Flag
Register – TIFR
1041H–11/01
• Bit 5 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt
(at vector $005) is executed if a capture-triggering event occurs on pin 20, PD6 (ICP)
(i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
• Bit 4 – OCIE1A: Timer/Counter1 Output CompareA Match Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at
vector $006) is executed if a CompareA match in Timer/Counter1 occurs (i.e., when the
OCF1A bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
• Bit 3 – OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at
vector $007) is executed if a CompareB match in Timer/Counter1 occurs (i.e., when the
OCF1B bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow Interrupt is enabled. The corresponding interrupt (at vector
$008) is executed if an overflow in Timer/Counter1 occurs (i.e., when the TOV1 bit is set
in the Timer/Counter Interrupt Flag Register [TIFR]).
• Bit 1 – Res: Reserved Bit
This bit is a reserved bit in the AT90S8535 and always reads zero.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow Interrupt is enabled. The corresponding interrupt (at vector
$009) is executed if an overflow in Timer/Counter0 occurs (i.e., when the TOV0 bit is set
in the Timer/Counter Interrupt Flag Register [TIFR]).
• Bit 7 – OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when compare match occurs between the Timer/Counter2
and the data in OCR2 (Output Compare Register2). OCF2 is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by
writing a logical “1” to the flag. When the I-bit in SREG and OCIE2 (Timer/Counter2
Compare Match Interrupt Enable) and the OCF2 are set (one), the Timer/Counter2
Compare Match Interrupt is executed.
• Bit 6 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV2 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE2
(Ti mer /Counter 2 O v erfl ow Inte rr upt Enabl e) and TOV 2 ar e s et ( one ), the
Timer/Counter2 Overflow Interrupt is executed. In up/down PWM mode, this bit is set
when Timer/Counter1 advances from $0000.
Bit
$38 ($58)
Read/Write
Initial Value
OCF2
R/W
7
0
TOV2
R/W
6
0
ICF1
R/W
5
0
OCF1A
R/W
4
0
OCF1B
R/W
3
0
TOV1
R/W
2
0
AT90S/LS8535
R
1
–
0
TOV0
R/W
0
0
TIFR
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